音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

DS90CR486 Datasheet

  • DS90CR486

  • 133MHz 48-Bit Channel Lick Deserializer (6.384 Gbps)

  • 348.29KB

  • 15頁(yè)

  • NSC

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書(shū)

PDF預(yù)覽

DS90CR486 133MHz 48-Bit Channel Link Deserializer (6.384 Gbps)
March 2003
DS90CR486
133MHz 48-Bit Channel Link Deserializer (6.384 Gbps)
General Description
The DS90CR486 receiver converts eight Low Voltage Differ-
ential Signaling (LVDS) data streams back into 48 bits of
LVCMOS/LVTTL data. Using a 133MHz clock, the data
throughput is 6.384Gbit/s (798Mbytes/s).
The multiplexing of data lines provides a substantial cable
reduction. Long distance parallel single-ended buses typi-
cally require a ground wire per active signal (and have very
limited noise rejection capability). Thus, for a 48-bit wide
data and one clock, up to 98 conductors are required. With
this Channel Link chipset as few as 19 conductors (8 data
pairs, 1 clock pair and a minimum of one ground) are
needed. This provides an 80% reduction in interconnect
width, which provides a system cost savings, reduces con-
nector physical size and cost, and reduces shielding require-
ments due to the cables鈥?smaller form factor.
The DS90CR486 deserializer is improved over prior genera-
tions of Channel Link devices and offers higher bandwidth
support and longer cable drive with three areas of enhance-
ment. To increase bandwidth, the maximum clock rate is
increased to 133 MHz and 8 serialized LVDS outputs are
provided. Cable drive is enhanced with a user selectable
pre-emphasis (on DS90CR485) feature that provides addi-
tional output current during transitions to counteract cable
loading effects. Optional DC balancing on a cycle-to-cycle
basis, is also provided to reduce ISI (Inter-Symbol Interfer-
ence). With pre-emphasis and DC balancing, a low distortion
eye-pattern is provided at the receiver end of the cable. A
cable deskew capability has been added to deskew long
cables of pair-to-pair skew. These three enhancements allow
long cables to be driven.
The DS90CR486 is intended to be used with the
DS90CR485 Channel Link Serializer. It is also backward
compatible with serializers DS90CR481 and DS90CR483.
The DS90CR486 is footprint compatible with the
DS90CR484.
The chipset is an ideal solution to solve EMI and intercon-
nect size problems for high-throughput point-to-point appli-
cations.
For more details, please refer to the 鈥淎pplications Informa-
tion鈥?section of this datasheet.
Features
n
n
n
n
n
n
n
n
n
n
n
Up to 6.384 Gbps throughput
66MHz to 133MHz input clock support
Reduces cable and connector size and cost
Cable Deskew function
DC balance reduces ISI distortion
For point-to-point backplane or cable applications
Low power, 890 mW typ at 133MHz
Flow through pinout for easy PCB design
+3.3V supply voltage
100-pin TQFP package
Conforms to TIA/EIA-644-A-2001 LVDS Standard
Generalized Block Diagram
20025203
漏 2003 National Semiconductor Corporation
DS200252
www.national.com

DS90CR486相關(guān)型號(hào)PDF文件下載

您可能感興趣的PDF文件資料

熱門(mén)IC型號(hào)推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫(kù)提出的寶貴意見(jiàn)，您的參與是維庫(kù)提升服務(wù)的動(dòng)力！意見(jiàn)一經(jīng)采納，將有感恩紅包奉上哦！