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DS90CF388AVJD Datasheet

  • DS90CF388AVJD

  • Dual Pixel LVDS Display Interface / FPD-Link

  • 412.87KB

  • 19頁

  • NSC

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DS90C387A/DS90CF388A Dual Pixel LVDS Display Interface / FPD-Link
October 2002
DS90C387A/DS90CF388A
Dual Pixel LVDS Display Interface / FPD-Link
General Description
The DS90C387A/DS90CF388A transmitter/receiver pair is
designed to support dual pixel data transmission between
Host and Flat Panel Display up to QXGA resolutions. The
transmitter converts 48 bits (Dual Pixel 24-bit color) of
CMOS/TTL data and 3 control bits into 8 LVDS (Low Voltage
Differential Signalling) data streams. At a maximum dual
pixel rate of 112MHz, LVDS data line speed is 784Mbps,
providing a total throughput of 5.7Gbps (714 Megabytes per
second).
The LDI chipset is improved over prior generations of
FPD-Link devices and offers higher bandwidth support and
longer cable drive. To increase bandwidth, the maximum
pixel clock rate is increased to 112 MHz and 8 serialized
LVDS outputs are provided. Cable drive is enhanced with a
user selectable pre-emphasis feature that provides addi-
tional output current during transitions to counteract cable
loading effects.
The DS90C387A transmitter provides a second LVDS output
clock. Both LVDS clocks are identical. This feature supports
backward compatibility with the previous generation of
FPD-Link Receivers - the second clock allows the transmit-
ter to interface to panels using a 鈥檇ual pixel鈥?configuration of
two 24-bit or 18-bit FPD-Link receivers.
This chipset is an ideal means to solve EMI and cable size
problems for high-resolution flat panel applications. It pro-
vides a reliable interface based on LVDS technology that
delivers the bandwidth needed for high-resolution panels
while maximizing bit times, and keeping clock rates low to
reduce EMI and shielding requirements. For more details,
please refer to the 鈥淎pplications Information鈥?section of this
datasheet.
Features
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Supports SVGA through QXGA panel resolutions
32.5 to 112/170MHz clock support
Drives long, low cost cables
Up to 5.7 Gbps bandwidth
Pre-emphasis reduces cable loading effects
Dual pixel architecture supports interface to GUI and
timing controller; optional single pixel transmitter inputs
support single pixel GUI interface
Transmitter rejects cycle-to-cycle jitter
5V tolerant on data and control input pins
Programmable transmitter data and control strobe select
(rising or falling edge strobe)
Backward compatible with FPD-Link
Compatible with ANSI/TIA/EIA-644-1995 LVDS Standard
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Generalized Transmitter Block Diagram
10132002
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
漏 2002 National Semiconductor Corporation
DS101320
www.national.com

DS90CF388AVJD 產(chǎn)品屬性

  • National Semiconductor (TI)

  • 48

  • 8

  • 5700 Mbps

  • 3.3 V

  • 2800 mW

  • + 70 C

  • TQFP-100

  • Tray

  • - 10 C

  • SMD/SMT

  • 3.6 V

  • 3 V

  • CMOS, TTL

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