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DS90CF383MTD Datasheet

  • DS90CF383MTD

  • +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link...

  • 9頁

  • NSC

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DS90CF383 +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link鈥?65 MHz
January 2000
DS90CF383
+3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD)
Link鈥?65 MHz
General Description
The DS90CF383 transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in par-
allel with the data streams over a fifth LVDS link. Every cycle
of the transmit clock 28 bits of input data are sampled and
transmitted. At a transmit clock frequency of 65 MHz, 24 bits
of RGB data and 3 bits of LCD timing and control data
(FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455
Mbps per LVDS data channel. Using a 65 MHz clock, the
data throughputs is 227 Mbytes/sec.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
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20 to 65 MHz shift clock support
Single 3.3V supply
Chipset (Tx + Rx) power consumption
<
250 mW (typ)
Power-down mode (
<
0.5 mW total)
Single pixel per clock XGA (1024x768) ready
Supports VGA, SVGA, XGA and higher addressability.
Up to 227 Megabytes/sec bandwidth
Up to 1.8 Gbps throughput
Narrow bus reduces cable size and cost
290 mV swing LVDS devices for low EMI
PLL requires no external components
Low profile 56-lead TSSOP package
Falling edge data strobe Transmitter
Compatible with TIA/EIA-644 LVDS standard
ESD rating
>
7 kV
Operating Temperature: 鈭?0藲C to +85藲C
Block Diagram
DS90CF383
DS100033-1
Order Number DS90CF383MTD
See NS Package Number MTD56
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
漏 2000 National Semiconductor Corporation
DS100033
www.national.com

DS90CF383MTD 產(chǎn)品屬性

  • National Semiconductor (TI)

  • 4

  • 28

  • 227 Mbps

  • 3.3 V

  • 1630 mW

  • + 85 C

  • TSSOP-56

  • Tube

  • - 40 C

  • SMD/SMT

  • 3.6 V

  • 3 V

  • LVDS

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