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DS90C402 Datasheet

  • DS90C402

  • Dual Low Voltage Differential Signaling (LVDS) Receiver

  • 136.98KB

  • 8頁

  • NSC

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DS90C402 Dual Low Voltage Differential Signaling (LVDS) Receiver
June 1998
DS90C402
Dual Low Voltage Differential Signaling (LVDS) Receiver
General Description
The DS90C402 is a dual receiver device optimized for high
data rate and low power applications. This device along with
the DS90C401 provides a pair chip solution for a dual high
speed point-to-point interface. The device is in a PCB space
saving 8 lead small outline package. The receiver offers
鹵
100 mV threshold sensitivity, in addition to common-mode
noise protection.
Features
n
n
n
n
n
n
Ultra Low Power Dissipation
Operates above 155.5 Mbps
Standard TIA/EIA-644
8 Lead SOIC Package saves PCB space
V
CM
鹵
1V center around 1.2V
鹵
100 mV Receiver Sensitivity
Connection Diagram
DS100006-1
Order Number DS90C402M
See NS Package Number M08A
Functional Diagram
DS100006-2
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
漏 1998 National Semiconductor Corporation
DS100006
www.national.com

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