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DS90C383SLC Datasheet

  • DS90C383SLC

  • +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Displa...

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  • NSC

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DS90C383/DS90CF384 +3.3V Programmable LVDS 24-Bit-Color Flat Panel Display (FPD)
Link鈥?5 MHz
November 2000
DS90C383/DS90CF384
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel
Display (FPD) Link鈥?5 MHz, +3.3V LVDS Receiver
24-Bit Flat Panel Display (FPD) Link鈥?5 MHz
General Description
The DS90C383 transmitter converts 28 bits of LVCMOS/
LVTTL data into four LVDS (Low Voltage Differential Signal-
ing) data streams. A phase-locked transmit clock is transmit-
ted in parallel with the data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bits of input data are
sampled and transmitted. The DS90CF384 receiver con-
verts the LVDS data streams back into 28 bits of LVCMOS/
LVTTL data. At a transmit clock frequency of 65 MHz, 24 bits
of RGB data and 3 bits of LCD timing and control data
(FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455
Mbps per LVDS data channel. Using a 65 MHz clock, the
data throughputs is 227 Mbytes/sec. The transmitter is of-
fered with programmable edge data strobes for convenient
interface with a variety of graphics controllers. The transmit-
ter can be programmed for Rising edge strobe or Falling
edge strobe through a dedicated pin. A Rising edge trans-
mitter will inter-operate with a Falling edge receiver
(DS90CF384) without any translation logic. Both devices are
also offered in a 64 ball, 0.8mm fine pitch ball grid array
(FBGA) package which provides a 44 % reduction in PCB
footprint compared to the TSSOP package.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n
20 to 65 MHz shift clock support
n
Programmable transmitter (DS90C383) strobe select
(Rising or Falling edge strobe)
n
Single 3.3V supply
n
Chipset (Tx + Rx) power consumption
<
250 mW (typ)
n
Power-down mode (
<
0.5 mW total)
n
Single pixel per clock XGA (1024x768) ready
n
Supports VGA, SVGA, XGA and higher addressability.
n
Up to 227 Megabytes/sec bandwidth
n
Up to 1.8 Gbps throughput
n
Narrow bus reduces cable size and cost
n
290 mV swing LVDS devices for low EMI
n
PLL requires no external components
n
Low profile 56-lead TSSOP package.
n
Also available in a 64 ball, 0.8mm fine pitch ball grid
array (FBGA) package
n
Falling edge data strobe Receiver
n
Compatible with TIA/EIA-644 LVDS standard
n
ESD rating
>
7 kV
n
Operating Temperature: 鈭?0藲C to +85藲C
Block Diagrams
Typical Application
DS012887-2
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
漏 2000 National Semiconductor Corporation
DS012887
www.national.com

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