DS90C3201 3.3V 8 MHz to 135 MHz Dual FPD-Link Transmitter
ADVANCE INFORMATION
April 2005
DS90C3201
3.3V 8 MHz to 135 MHz Dual FPD-Link Transmitter
General Description
The DS90C3201 is a 3.3V single/dual FPD-Link 10-bit color
transmitter is designed to be used in Liquid Crystal Display
TVs, LCD Monitors, Digital TVs, and Plasma Display Panel
TVs. The DS90C3201 is designed to interface between the
digital video processor and the display device using the
low-power, low-EMI LVDS (Low Voltage Differential Signal-
ing) interface. The DS90C3201 converts up to 70 bits of
LVCMOS/LVTTL data into ten LVDS data streams. The
transmitter can be programmed clocking data with rising
edge or falling edge clock. Optional two-wire serial program-
ming allows fine tuning in development and production en-
vironments. At a transmitted clock frequency of 135 MHz, 70
bits of LVCMOS/LVTTL data are transmitted at an effective
rate of 945 Mbps per LVDS channel. Using a 135 MHz clock,
the data throughput is 9.45Gbit/s (945Mbytes/s). This allows
the dual 10-bit LVDS Transmitter to support HDTV resolu-
tions.
Features
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Up to 9.45Gbit/s data throughput
8 MHz to 135 MHz input clock support
Supports up to QXGA panel resolutions
Supports HDTV resolutions and frame rates up to
1920 x 1080p
LVDS 30-bit, 24-bit or 18-bit color data outputs
Supports single pixel and dual pixel interfaces
Supports spread spectrum clocking
Two-wire serial communication interface
Programmable clock edge and control strobe select
Power down mode
+3.3V supply voltage
128-pin TQFP
Compliant to TIA/EIA-644-A-2001 LVDS Standard
Backward compatible configuration with FPD-Link
Block Diagram
20147201
FIGURE 1. Transmitter Block Diagram
漏 2005 National Semiconductor Corporation
DS201472
www.national.com
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