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DS42585 Datasheet

  • DS42585

  • Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

  • 905.29KB

  • 58頁

  • AMD

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PRELIMINARY
DS42585
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29DL324D Bottom Boot 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only,
Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
s
Power supply voltage of 2.7 to 3.3 volt
s
High performance
鈥?85 ns maximum access time
SOFTWARE FEATURES
s
Data Management Software (DMS)
鈥?AMD-supplied software manages data programming and
erasing, enabling EEPROM emulation
鈥?Eases sector erase limitations
s
Package
鈥?73-Ball FBGA
s
Supports Common Flash Memory Interface (CFI)
s
Erase Suspend/Erase Resume
鈥?Suspends erase operations to allow programming in same
bank
s
Operating Temperature
鈥?鈥?5擄C to +85擄C
Flash Memory Features
ARCHITECTURAL ADVANTAGES
s
Simultaneous Read/Write operations
鈥?Data can be continuously read from one bank while
executing erase/program functions in other bank
鈥?Zero latency between read and write operations
s
Data# Polling and Toggle Bits
鈥?Provides a software method of detecting the status of
program or erase cycles
s
Unlock Bypass Program command
鈥?Reduces overall programming time when issuing multiple
program command sequences
HARDWARE FEATURES
s
Any combination of sectors can be erased
s
Ready/Busy# output (RY/BY#)
鈥?Hardware method for detecting program or erase cycle
completion
s
Secured Silicon (SecSi) Sector: Extra 64 KByte sector
鈥?/div>
Factory locked and identifiable:
16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function.
鈥?/div>
Customer lockable:
Can be read, programmed, or erased
just like other sectors. Once locked, data cannot be changed
s
Hardware reset pin (RESET#)
鈥?Hardware method of resetting the internal state machine to
reading array data
s
Zero Power Operation
鈥?Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero
s
WP#/ACC input pin
鈥?Write protect (WP#) function allows protection of two outermost
boot sectors, regardless of sector protect status
鈥?Acceleration (ACC) function accelerates program timing
s
Bottom boot block
s
Manufactured on 0.23 碌m process technology
s
Compatible with JEDEC standards
鈥?Pinout and software compatible with single-power-supply
flash standard
s
Sector protection
鈥?Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
鈥?Temporary Sector Unprotect allows changing data in
protected sectors in-system
PERFORMANCE CHARACTERISTICS
s
High performance
鈥?Access time as fast 70 ns
鈥?Program time: 7 碌s/word typical utilizing Accelerate function
SRAM Features
s
Power dissipation
鈥?Operating: 50 mA maximum
鈥?Standby: 7 碌A maximum
s
Ultra low power consumption (typical values)
鈥?2 mA active read current at 1 MHz
鈥?10 mA active read current at 5 MHz
鈥?200 nA in standby or automatic sleep mode
s
Minimum 1 million write cycles guaranteed per sector
s
20 Year data retention at 125擄C
鈥?Reliable operation for the life of the system
s
s
s
s
CE1s# and CE2s Chip Select
Power down features using CE1s# and CE2s
Data retention supply voltage: 1.5 to 3.3 volt
Byte data control: LB#s (DQ0鈥揇Q7), UB#s (DQ8鈥揇Q15)
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication#
25032
Rev:
A
Amendment/0
Issue Date:
May 22, 2001
Refer to AMD鈥檚 Website (www.amd.com) for the latest information.

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