DS3647A Quad TRI-STATE MOS Memory I O Register
February 1986
DS3647A Quad TRI-STATE MOS Memory I O Register
General Description
The DS3647A is a 4-bit I O buffer register intended for use
in MOS memory systems This circuit employs a fall-through
latch for data storage This method of latching captures the
data in parallel with the output thus eliminating the delays
encountered in other designs This circuit uses Schottky-
clamped transistor logic for minimum propagation delay and
employs PNP input transistors so that input currents are
low allowing a large fan-out for this circuit which is needed
in a memory system
Two pins per bit are provided and data transfer is bi-direc-
tional so that the register can handle both input and output
data The direction of data flow is controlled through the
input enables The latch control when taken low will cause
the register to hold the data present at that time and display
it at the outputs Data can be latched into the register inde-
pendent of the output disables or EXPANSION input Either
or both of the outputs may be taken to the high-impedance
state with the output disables The EXPANSION pin dis-
ables both outputs to facilitate multiplexing with other I O
registers on the same data lines
The DS3647A features TRI-STATE outputs The 鈥樷€楤鈥欌€?port
outputs are designed for use in bus organized data trans-
mission systems and can sink 80 mA and source
b
5 2 mA
Data going from port 鈥樷€楢鈥欌€?to port 鈥樷€楤鈥欌€?and from 鈥樷€楤鈥欌€?to port
鈥樷€楢鈥欌€?is inverted in the DS3647A
Features
Y
Y
Y
Y
Y
Y
Y
Y
PNP inputs minimize loading
Fall-through latch design
Propagation delay of only 15 ns
TRI-STATE outputs
EXPANSION control
Bi-directional data flow
TTL compatible
Transmission line driver output
Logic and Connection Diagrams
Dual-In-Line Package
TL F 8354 鈥?2
Top View
Order Number DS3647AD or DS3647AN
See NS Package Number D16C or N16A
TL F 8354 鈥?1
TRI-STATE is a registered trademark of National Semiconductor Corp
C
1995 National Semiconductor Corporation
TL F 8354
RRD-B30M105 Printed in U S A
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