DS3131DK
Bit-SynchronouS (BoSS)
HDLC Controller Demo Kit
www.maxim-ic.com
GENERAL DESCRIPTION
The DS3131 bit-synchronous (BoSS) HDLC
controller can handle up to 40 channels of high-
speed, unchannelized, bit-synchronous HDLC.
The on-board DMA has been optimized for
maximum flexibility and PCI bus efficiency to
minimize host processor intervention in the data
path. Diagnostic loopbacks and an on-board
BERT remove the need for external components.
FEATURES
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40 Timing Independent Ports
40 Bidirectional HDLC Channels
Each Port Can Operate Up to 52Mbps
Up to 132Mbps Full-Duplex Throughput
On-Board Bit Error-Rate Tester (BERT)
Diagnostic Loopbacks in Both Directions
Local Bus Supports PCI Bridging
33MHz 32-Bit PCI Interface
Full Suite of Driver Code
APPLICATIONS
Routers
xDSL Access Multiplexers (DSLAMs)
Clear-Channel (unchannelized) T1/E1
Clear-Channel (unchannelized) T3/E3
SONET/SDH Path Overhead Termination
High-Density V.35 Terminations
High-Speed Links such as HSSI
ORDERING INFORMATION
PART
DS3131
TEMP RANGE
0擄C to +70擄C
PIN-PACKAGE
272 PBGA
FUNCTIONAL DIAGRAM
RECEIVE DIRECTION
TRANSMIT DIRECTION
RC0
RD0
TC0
TD0
RC1
RD1
TC1
TD1
RC2
RD2
TC2
TD2
40-BIT SYNCHRONOUS
HDLC CONTROLLERS
PCLK
PRST
PAD[31:0]
PCBE[3:0]
PPAR
PFRAME
PIRDY
PTRDY
PSTOP
PIDSEL
PDEVSEL
PREQ
PGNT
PPERR
PSERR
PXAS
PXDS
PXBLAST
DMA BLOCK
RC39
RD39
TC39
TD39
LAYER 1 BLOCK
FIFO BLOCK
PCI BLOCK
LOCAL BUS BLOCK
INTERNAL CONTROL BUS
LA[19:0]
LD[15:0]
LWR(
LR
/W)
LRD(LDS)
LIM
BERT
DS3131
JTRST
JTDI
JTMS
JTCLK
JTDO
JTAG TEST
ACCESS
LINT
LRDY
LMS
LCS
LHOLD(LBR)
LHLDA(
LBG
)
LBGACK
LCLK
LBHE
LBPXS
PIN NAMES IN ( )
ARE ACTIVE WHEN
THE DEVICE IS IN
THE MOT MODE
(i.e., LIM = 1).
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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