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DS26502LN+ Datasheet

  • DS26502LN+

  • Framer, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, LQFP-64

  • 124頁

  • MAXIM   MAXIM

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DS26502
T1/E1/J1/64KCC BITS Element
www.maxim-ic.com
GENERAL DESCRIPTION
The DS26502 is a building-integrated timing-
supply (BITS) clock-recovery element. It also
functions as a basic T1/E1 transceiver. The
receiver portion can recover a clock from T1,
E1, 64kHz composite clock (64KCC), and
6312kHz synchronization timing interfaces. In
T1 and E1 modes, the Synchronization Status
Message (SSM) can also be recovered. The
transmit portion can directly interface to T1, E1,
or 64KCC synchronization interfaces as well as
source the SSM in T1 and E1 modes. The
DS26502 can translate between any of the
supported inbound synchronization clock rates to
any supported outbound rate. A separate output
is provided to source a 6312kHz clock. The
device is controlled through a parallel, serial, or
hardware controller port.
FEATURES
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APPLICATIONS
BITS Timing
Rate Conversion
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ORDERING INFORMATION
PART
DS26502L
DS26502LN
TEMP RANGE PIN-PACKAGE
0擄C to +70擄C
-40擄C to +85擄C
64 LQFP
64 LQFP
G.703 2048kHz Synchronization Interface
Compliant
G.703 64kHz Centralized (Option A) and
Codirectional Timing Interface Compliant
G.703 Appendix II 64kHz and 6312kHz
Japanese Synchronization Interface
Compliant
Interfaces to Standard T1/J1 (1.544MHz) and
E1 (2.048MHz)
Interface to CMI-Coded T1/J1 and E1
Short- and Long-Haul Line Interface
Transmit and Receive T1 and E1 SSM
Messages with Message Validation
T1/E1 Jitter Attenuator with Bypass Mode
Fully Independent Transmit and Receive
Functionality
Internal Software-Selectable Receive- and
Transmit-Side Termination for
75鈩?100鈩?110鈩?120鈩?T1, E1, and
Composite Clock Interfaces
Monitor Mode for Bridging Applications
Accepts 16.384MHz, 8.192MHz, 4.096MHz,
or 2.048MHz Master Clock
64kHz, 8kHZ, and 400Hz Outputs in
Composite Clock Mode
8-Bit Parallel Control Port, Multiplexed or
Nonmultiplexed, Intel or Motorola
Serial (SPI) Control Port
Hardware Control Mode
Provides LOS, AIS, and LOF Indications
Through Hardware Output Pins
Fast Transmitter-Output Disable Through
Device Pin for Protection Switching
IEEE 1149.1 JTAG Boundary Scan
3.3V Supply with 5V-Tolerant Inputs and
Outputs
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
1 of 124
REV: 032405

DS26502LN+ 產(chǎn)品屬性

  • Lead (SnPb) Finish for COTSObsolescence Mitigation Program

  • 160

  • 集成電路 (IC)

  • 時鐘/計時 - 專用

  • -

  • BITS 元件，多路復(fù)用器

  • 是

  • T1/E1

  • 時鐘

  • 時鐘

  • 1

  • 2:3

  • 無/無

  • 6.312MHz

  • 3.135 V ~ 3.465 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 64-LQFP

  • 64-LQFP（10x10）

  • 托盤

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