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Hysteresis Inputs to Improve Noise Immunity
2-Way Asynchronous Data Bus Communication
Input Diodes Limit High-Speed Termination Effects
ESD > 3500 Volts
LOGIC AND CONNECTION DIAGRAMS DIP
(TOP VIEW)
V
CC
20
E
19
B1
18
B2
17
B3
16
B4
15
B5
14
B6
13
B7
12
B8
11
LOW
POWER
SCHOTTKY
MARKING
DIAGRAMS
SN74LS245N
AWLYYWW
20
1
1
1
DIR
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
10
GND
PDIP鈥?0
N SUFFIX
CASE 738
TRUTH TABLE
INPUTS
OUTPUT
E
L
L
H
DIR
L
H
X
Bus B Data to Bus A
Bus A Data to Bus B
Isolation
1
1
20
LS245
AWLYYWW
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
SOIC鈥?0
DW SUFFIX
CASE 751D
GUARANTEED OPERATING RANGES
Symbol
V
CC
T
A
I
OH
Parameter
Supply Voltage
Operating Ambient
Temperature Range
Output Current 鈥?High
Min
4.75
0
Typ
5.0
25
Max
5.25
70
鈥?.0
鈥?5
I
OL
Output Current 鈥?Low
24
Unit
V
擄C
mA
mA
mA
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
SN74LS245N
SN74LS245DW
Package
PDIP鈥?0
SOIC鈥?0
Shipping
1440 Units/Box
2500/Tape & Reel
漏
Semiconductor Components Industries, LLC, 2000
1
August, 2000 鈥?Rev. 7
Publication Order Number:
SN74LS245/D