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DS2175N Datasheet

  • DS2175N

  • T1/CEPT Elastic Store

  • 12頁

  • DALLAS   DALLAS

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DS2175
T1/CEPT Elastic Store
www.dalsemi.com
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Rate buffer for T1 and CEPT transmission
systems
Synchronizes loop鈥搕imed and system timed
data streams on frame boundaries
Ideal for T1 (1.544 MHz) to CEPT (2.048
MHz), CEPT to T1 interfaces
Supports parallel and serial backplanes
Buffer depth is 2 frames
Comprehensive on鈥揷hip 鈥渟lip鈥?control logic
鈥?Slips occur only on frame boundaries
鈥?Outputs report slip occurrences and
direction
鈥?Align feature allows buffer to be recentered
at any time
鈥?Buffer depth easily monitored
Compatible with DS2180A T1 and DS2181A
CEPT Transceivers
Industrial temperature range of 鈥?0擄C to
+85擄C available, designated DS2175N
PIN ASSIGNMENT
RCLKSEL
RCLK
RSER
RMSYNC
FSD
SLIP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
SYSCLK
SSER
SMSYNC
SFSYNC
SCHCLK
S/P
SCLKSEL
ALN
VSS
鈥?/div>
鈥?/div>
16-PIN DIP (300 MIL)
16-PIN SOIC (300 MIL)
DESCRIPTION
The DS2175 is a low鈥損ower CMOS elastic鈥搒tore memory optimized for use in primary rate telecommu-
nications transmission equipment. The device serves as a synchronizing element between async data
streams and is compatible with North American (T1鈥?.544 MHz) and European (CEPT鈥?.048 MHz) rate
networks. The chip has several flexible operating modes which eliminate support logic and hardware cur-
rently required to interconnect parallel or serial TDM backplanes. Application areas include digital
trunks, drop and insert equipment, digital cross鈥揷onnects (DACS), private network equipment and
PABX鈥搕o鈥揷omputer interfaces such as DMI and CPI.
1 of 12
092099

DS2175N 產(chǎn)品屬性

  • Lead (SnPb) Finish for COTSObsolescence Mitigation Program

  • 25

  • 集成電路 (IC)

  • 接口 - 信號緩沖器，中繼器，分配器

  • -

  • 存儲器

  • T1/CEPT

  • 100ns

  • 5pF

  • 4.5 V ~ 5.5 V

  • 9mA

  • 通孔

  • 16-DIP（0.300"，7.62mm）

  • 16-PDIP

  • 管件

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