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DS21552L Datasheet

  • DS21552L

  • 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers

  • 137頁

  • DALLAS   DALLAS

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3.3V DS21352 and 5V DS21552
T1 Single-Chip Transceivers
www.maxim-ic.com
FEATURES
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Complete DS1/ISDN鈥揚RI/J1 transceiver functionality
Long and Short haul LIU
Crystal鈥搇ess jitter attenuator
Generates DSX鈥? and CSU line build-outs
HDLC controller with 64-byte buffers Configurable for
FDL or DS0 operation
Dual two鈥揻rame elastic store slip buffers that can
connect to asynchronous backplanes up to 8.192MHz
8.192MHz clock output locked to RCLK
Interleaving PCM Bus Operation
Per-channel loopback and idle code insertion
8-bit parallel control port muxed or nonmuxed buses
(Intel or Motorola)
Programmable output clocks for Fractional T1
Fully independent transmit and receive functionality
Generates/detects in-band loop codes from 1 to 8 bits
in length including CSU loop codes
IEEE 1149.1 JTAG-Boundary Scan
Pin compatible with DS2152/54/354/554 SCTs
100-pin LQFP package (14 mm x 14 mm) 3.3V
(DS21352) or 5V (DS21552) supply; low power
CMOS
PIN ASSIGNMENT
DS21352
DS21552
100
1
ORDERING INFORMATION
DS21352L
DS21352LN
DS21552L
DS21552LN
(0擄C to +70擄C)
(-40擄C to +85擄C)
(0擄C to +70擄C)
(-40擄C to +85擄C)
DESCRIPTION
The DS21352/552 T1 single-chip transceiver contains all of the necessary functions for connection to T1
lines whether they are DS1 long haul or DSX鈥? short haul. The clock recovery circuitry automatically
adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both DSX鈥? line build
outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. The onboard jitter attenuator
(selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The
framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also
used for extracting and inserting robbed-bit signaling data and FDL data. The device contains a set of
internal registers which the user can access and control the operation of the unit. Quick access via the
parallel control port allows a single controller to handle many T1 lines. The device fully meets all of the
latest T1 specifications including ANSI T1.403-1995, ANSI T1.231-1993, AT&T TR 62411 (12鈥?0),
AT&T TR54016, and ITU G.703, G.704, G.706, G.823, and I.431.
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120501

DS21552L 產(chǎn)品屬性

  • Lead (SnPb) Finish for COTS

  • 90

  • 集成電路 (IC)

  • 接口 - 電信

  • -

  • 單芯片收發(fā)器

  • E1，HDLC，J1，T1

  • 1

  • 4.75 V ~ 5.25 V

  • 75mA

  • -

  • 0°C ~ 70°C

  • 表面貼裝

  • 100-LQFP

  • 100-LQFP（14x14）

  • 托盤

  • DSX-1 和 CSU 線路補償發(fā)生器，HDLC 控制器，帶內(nèi)回路代碼發(fā)生器和檢測器

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