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DS2151 Datasheet

  • DS2151

  • T1 Single-Chip Transceiver

  • 1100.53KB

  • 51頁

  • DALLAS   DALLAS

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DS2151Q
T1 Single-Chip Transceiver
www.dalsemi.com
FEATURES
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Complete DS1/ISDN-PRI transceiver
functionality
Line interface can handle both long- and
short-haul trunks
32-bit or 128-bit jitter attenuator
Generates DSX-1 and CSU line build outs
Frames to D4, ESF, and SLC-96
R
formats
Dual onboard two-frame elastic store slip
buffers that connect to backplanes up to 8.192
MHz
8-bit parallel control port that can be used on
either multiplexed or non-multiplexed buses
Extracts and inserts Robbed-Bit signaling
Detects and generates yellow and blue alarms
Programmable output clocks for Fractional T1
Fully independent transmit and receive
functionality
Onboard FDL support circuitry
Generates and detects CSU loop codes
Contains ANSI one鈥檚 density monitor and
enforcer
Large path and line error counters including
BPV, CV, CRC6, and framing bit errors
Pin compatible with DS2153Q E1 Single-
Chip Transceiver
5V supply; low power CMOS
Industrial grade version (-40擄C to +85擄C)
available (DS2151QN)
PIN ASSIGNMENT
FUNCTIONAL BLOCKS
LONG & SHORT
HAUL LINE
INTERFACE
FRAMER
PARALLEL CONTROL
PORT
Dallas
DS2151Q
T1SCT
ACTUAL SIZE OF 44-PIN PLCC
TCHCLK
40
39
38
37
36
35
34
33
32
31
30
29
19
20
21
22
23
24
25
26
27
28
AD7
AD6
AD5
AD4
AD3
AD2
43
AD1
42
ALE
WR
RLINK
RLCLK
DVSS
RCLK
RCHCLK
RSER
RSYNC
RLOS/LOTC
SYSCLK
44
41
6
5
4
3
2
1
AD0
RD
CS
ELASTIC
STORES
7
8
9
10
11
12
13
14
15
16
17
18
TSER
TCLK
DVDD
TSYNC
TLINK
TLCLK
TCHBLK
TRING
TVDD
TVSS
TTIP
INT1
XTAL1
RRING
DESCRIPTION
The DS2151Q T1 Single-Chip Transceiver (SCT) contains all of the necessary functions for connection
to T1 lines whether they be DS-1 long haul or DSX-1 short haul. The clock recovery circuitry
automatically adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both
DSX-1 line build outs as well as CSU build outs of -7.5 dB, -15 dB, and -22.5 dB. The onboard jitter
attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data
paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms.
It is also used for extracting and inserting Robbed-Bit signaling data and FDL data. The device contains
a set of 64 8-bit internal registers which the user can access to control the operation of the unit. Quick
access via the parallel control port allows a single micro to handle many T1 lines. The device fully meets
all of the latest T1 specifications including ANSI T1.403-199X, AT&T TR 62411 (12-90), and ITU
G.703, G.704, G.706, G.823, and I.431.
1 of 51
081099
RCHBLK
XTAL2
ACLKI
RTIP
RVDD
RVSS
INT2
BTS

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