PDF預(yù)覽

• 1
• 2
• 3
• 4
• 5
• 6
• 7
• 8
• 9
• 10
• 11
• 12
• 13
• 14
• 15
• 16

DS1WM

Synthesizable 1-Wire Bus Master

www.maxim-ic.com

FEATURES

摟

摟

摟

摟

摟

摟

摟

摟

摟

Memory maps into any standard byte-wide

data bus.

Eliminates CPU 鈥渂it-banging鈥?by internally

generating all 1-Wire

廬

timing and control

signals.

Generates interrupts to provide for more

efficient programming.

Search ROM Accelerator relieves CPU from

any single bit operations on the 1-Wire Bus.

Supports Overdrive mode and slave

interrupts.

Capable of running off any system clock from

3.2MHz to 128MHz.

Small size: all digital design, only 1500 gates.

Available in both Verilog and VHDL.

Applications include any circuit containing a

1-Wire communication bus.

Customer ASIC

Internal

Data Bus

1-Wire

Master

1-Wire

Bus

Interrupt

DESCRIPTION

As more 1-Wire devices become available, more and more users have to deal with the demands of

generating 1-Wire signals to communicate to them. This usually requires 鈥渂it-banging鈥?a port pin on a

microprocessor, and having the microprocessor perform the timing functions required for the 1-Wire

protocol. While 1-Wire transmission can be interrupted mid-byte, it cannot be interrupted during the

鈥渓ow鈥?time of a bit time slot; this means that a CPU will be idled for up to 60 microseconds for each bit

sent and at least 480 microseconds when generating a 1-Wire reset. The 1-Wire Master helps users handle

communication to 1-Wire devices in their system without tying up valuable CPU cycles. Integrated into a

user鈥檚 ASIC as a 1-Wire port, the core is available in both VHDL and Verilog code and uses very little

chip area (1492 gates plus 1 bond pad for the Verilog version).

This circuit is designed to be memory mapped into the user鈥檚 system and provides complete control of the

1-Wire bus through 8 bit commands. The host CPU loads commands, reads and writes data, and sets

interrupt control through five individual registers. All of the timing and control of the 1-Wire bus are

generated within. The host merely needs to load a command or data and then may go on about its

business. When bus activity has generated a response that the CPU needs to receive, the 1-Wire Master

sets a status bit and, if enabled, generates an interrupt to the CPU. In addition to write and read

simplification, the 1-Wire Master also provides a Search ROM Accelerator function relieving the CPU

from having to perform any single-bit operations on the 1-Wire bus.

1-Wire is a registered trademark of Dallas Semiconductor.

1 of 15

031902

next

DS1WM相關(guān)型號PDF文件下載

• 型號
  版本
  描述
  廠商
  下載
• DS1WM
  英文版
  Synthesizable 1-WireTM Bus Master
  
  DS1WM

您可能感興趣的PDF文件資料

• DS1WM

熱門IC型號推薦

• DTA144TKA T146
• DTA144EETL
• DRV632PWR
• DS1210S
• DS1489AMX
• DAC900E
• DAC7624U
• DS1834A
• DS14C535MSA
• DS96174CN
• DS34C86TM
• DM9161EP