鈥?/div>
Three
interrupts are separately software-maskable
and testable
鈥?Time-of-day alarm once/second to once/day
鈥?Periodic rates from 122
ms
to 500 ms
鈥?End of clock update cycle
DESCRIPTION
The DS1287A is identical to the DS1287 with the addi-
tion of the RAM clear pin. For a complete description of
operating conditions, electrical and mechanical charac-
teristics, bus timing, and pin descriptions see the
DS12887A data sheet.
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