The DS1267 consist of two digitally controlled solid鈥?/div>
state potentiometers. Each potentiometer is composed
of 256 resistive sections. Between each resistive sec-
tion and both ends of the potentiometer are tap points
which are accessible to the wiper. The position of the
wiper on the resistive array is set by an 8鈥揵it value that
controls which tap point is connected to the wiper output.
Communication and control of the device is accom-
plished via a 3鈥搘ire serial port interface. This interface
allows the device wiper position to be read or written.
Both potentiometers can be connected in series (or
stacked) for an increased total resistance with the same
resolution. For multiple device鈥搒ingle processor envi-
ronments, the DS1267 can be cascaded or daisy
chained. This feature provides for control of multiple
devices over a single 3鈥搘ire bus.
20鈥揚in TSSOP (173 Mil)
PIN DESCRIPTION
L0, L1
H0, H1
W0, W1
V
B
S
OUT
RST
DQ
CLK
C
OUT
V
CC
GND
NC
DNC
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Low End of Resistor
High End of Resistor
Wiper Terminal of Resistor
Substrate Bias Voltage
Stacked Configuration Output
Serial Port Reset Input
Serial Port Data Input
Serial Port Clock Input
Cascade Port Output
+5 Volt Supply
Ground
No Internal Connection
Do Not Connect
ECopyright
1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor databooks.
052694 1/11
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