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DS1231S Datasheet

  • DS1231S

  • Power Monitor Chip

  • 9頁

  • DALLAS   DALLAS

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DS1231/S
DS1231/S
Power Monitor Chip
FEATURES
PIN ASSIGNMENT
IN
MODE
TOL
GND
1
2
3
4
8
7
6
5
VCC
NMI
RST
RST
鈥?/div>
Warns processor of an impending power failure
鈥?/div>
Provides time for an orderly shutdown
鈥?/div>
Prevents
processor from destroying nonvolatile
memory during power transients
restarts processor after power is
DS1231 8鈥揚in DIP
(300 MIL)
See Mech. Drawings
Section
NC
IN
NC
MODE
NC
TOL
NC
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
VCC
NC
NMI
NC
RST
NC
RST
鈥?/div>
Automatically
restored
鈥?/div>
Suitable for linear or switching power supplies
鈥?/div>
Adjusts to hold time of the power supply
鈥?/div>
Supplies necessary signals for processor interface
鈥?/div>
Accurate 5% or 10% V
CC
monitoring
鈥?/div>
Replaces power-up reset circuitry
鈥?/div>
No external capacitors required
鈥?/div>
Optional 16-pin SOIC surface mount package
DS1231S 16鈥揚in SOIC
(300 MIL)
See Mech. Drawings
Section
PIN DESCRIPTION
IN
MODE
TOL
GND
RST
RST
NMI
V
CC
NC
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Input
Selects input pin characteristics
Selects 5% or 10% V
CC
detect
Ground
Reset (Active High)
Reset (Active Low, open drain)
Non鈥揗askable Interrupt
+5V Supply
No Connections
DESCRIPTION
The DS1231 Power Monitor Chip uses a precise tem-
perature-compensated reference circuit which provides
an orderly shutdown and an automatic restart of a pro-
cessor-based system. A signal warning of an impending
power failure is generated well before regulated DC
voltages go out of specification by monitoring high volt-
age inputs to the power supply regulators. If line isola-
tion is required a UL-approved opto-isolator can be di-
rectly interfaced to the DS1231. The time for processor
shutdown is directly proportional to the available
hold-up time of the power supply. Just before the
hold-up time is exhausted, the Power Monitor uncondi-
tionally halts the processor to prevent spurious cycles
by enabling Reset as V
CC
falls below a selectable 5 or
10 percent threshold. When power returns, the proces-
sor is held inactive until well after power conditions have
stabilized, safeguarding any nonvolatile memory in the
system from inadvertent data changes.
022698 1/9

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