16Mx16, 7.5 - 15ns, P12, M-Densus
30A232-00
A
256 Megabit Synchronous DRAM
DPSD16MX16TY5
High Density Memory Device
ADVANCED INFORMATION
DESCRIPTION:
The
M-Densus
series is a family of interchangeable memory modules. The 256 Megabit SDRAM is a member of
this family which utilizes the new and innovative space saving TSOP stacking technology. The modules are
constructed with 8 Meg x 16 SDRAMs.
This 128 Megabit based
M-Densus
module, the
DPSD16MX16TY5 has been designed to fit in the same
footprint as the 8 Meg x 16 SDRAM TSOP monolithic and
128 Megabit SDRAM based family of
M-Densus
modules.
This allows the memory board designer to upgrade the
memory in their products without redesigning the
memory board, thus saving time and money.
FEATURES:
鈥?/div>
Configuration Available:
16 Meg x 16 bit (with two Chip Selects)
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Clock Frequency:
66
[1]
, 83
[1]
, 100, 125
[2]
, 133
[2]
MHz (max.)
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PC100 and PC133 Compatible
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3.3V Supply
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LVTTL Compatible I/O
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Four Bank Operation
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Programmable Burst Type, Burst Length,
and CAS Latency
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4096 Cycles / 64 ms
鈥?/div>
Auto and Self Refresh
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Package: TSOP Leadless Stack
NOTES: [1] Available in Industrial Temperature Ranges Only.
[2] Available in Commercial Temperature Range Only.
M-Densus
PIN-OUT DIAGRAM
PIN NAMES
A0 - A11
BA0, BA1
DQ0 - DQ15
CAS
RAS
WE
UDQM,
LDQM
CKE
CLK
CS0-CS1
V
CC
/V
SS
V
CCQ
/V
SSQ
N.C./RFU
Row Address:
A0 - A11
Column Address: A0 - A8
Bank Select Address
Data In / Data Out
Column Address Strobes
Row Address Enables
Data Write Enable
Upper & Lower
Data Input/Output Mask
Clock Enable
System Clock
Chip Selects
Power Supply/Ground
Data Output Power/Ground
No Connect
Reserved for Future Use
FUNCTIONAL BLOCK DIAGRAM
30A232-00
REV. A
This document contains information on a product under consideration for
development at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right
to change or discontinue information on this product without prior notice.
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