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DP84900 Datasheet

  • DP84900

  • 12頁(yè)

  • ETC

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DP84900
PRELIMINARY
June 1993
DP84900 1 7 Encoder Decoder Circuit
General Description
The DP84900 is designed to perform the encoding and de-
coding for disk memory systems It is designed to interface
directly with National Semiconductor鈥檚 integrated read
channel circuits such as the DP8492 This Encoder
Decoder (ENDEC) circuit employs a 2 3 (1 7) Run Length
Limited (RLL) code type and supports hard sectored format
The ENDEC also includes write data precompensation cir-
cuitry which detects the need for precompensation This cir-
cuitry issues early late and level (PCOMP3T) output signals
necessary for two levels of precompensation Precompen-
sation information is generated against both the 2T and 3T
patterns The precompensation circuitry can be bypassed
by the setting of a bit in the control register
A control register is included to configure the ENDEC and to
select several device operation options such as output code
inversion and TRI-STATE of the NRZ output
The DP84900 is available in a 20-pin SO and SSO package
1 7 Encoder Decoder Circuit
Features
Y
Y
Y
Y
Y
Y
Y
Y
Operates at Non-Return to Zero (NRZ) data rates up to
25 Mbits second
Single
a
5V power supply operation
Low Power dissipation 110 mW at 25 Mbits sec NRZ
rate
TTL compatible inputs and outputs
Supports write data precompensation with Early Late
and Level (PCOMP3T) output signals
Power Down Mode included
DC-erasure is available to support analog flaw map
testing
Bypass mode available which permits un-encoded test
patterns to be issued at the CODEOUT pin
Block Diagram
TL F 11420 鈥?1
FIGURE 1 ENDEC Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
IBM is a registered trademark of International Business Machines Corporation
C
1995 National Semiconductor Corporation
TL F 11420
RRD-B30M105 Printed in U S A

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