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DP84322 Datasheet

  • DP84322

  • 16頁

  • ETC

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DP84322 Dynamic RAM Controller Interface Circuit for the 68000 CPU
March 1986
DP84322 Dynamic RAM Controller Interface Circuit
for the 68000 CPU
General Description
The DP84322 dynamic RAM controller interface is a Pro-
grammable Array Logic (PAL ) device which allows for easy
interface between the DP8409A 17 18 19 28 29 dynamic
RAM Controllers and the 68000 008 010 microprocessors
The DP84322 supplies all the control signals needed to per-
form memory read write and refresh Logic is included for
inserting a wait state when using fast CPUs
Features
Y
Y
Y
Y
Y
Y
Y
Y
Provides 3-chip solution for the 68000 CPU and dynam-
ic RAM interface (DP84300 DP84322
DP8409A)
Works with all 68000 speed versions
Possibility of operation at 8 MHz with no wait states
Performs hidden refresh
DTACK is automatically inserted for both memory ac-
cess and memory refresh
Performs forced refresh using typically 4 CPU clocks
Standard National Semiconductor PAL part
(DMPAL16R4)
PAL logic equations can be modified by the user for his
specific application and programmed into any of the
PAL in the National Semiconductor PAL family includ-
ing the new high speed PALs
Connection and Block Diagrams
Dual-In-Line Package
TL F 5003鈥?
Top View
Order Number DP84322J or DP84322N
See NS Package Number J20A or N20A
TL F 5003 鈥?2
TRI-STATE is a registered trademark of National Semiconductor Corp
PAL is a registered trademark of and used under license from Monolithic Memories Inc
C
1995 National Semiconductor Corporation
TL F 5003
RRD-B30M75 Printed in U S A

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