音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

DP8429V-70 Datasheet

  • DP8429V-70

  • 1 Megabit High Speed Dynamic RAM Controller/Drivers

  • 26頁

  • NSC

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

DP8428 NS32828 DP8429 NS32829
1 Megabit High Speed Dynamic RAM Controller Drivers
September 1991
DP8428 NS32828 DP8429 NS32829
1 Megabit High Speed Dynamic RAM Controller Drivers
General Description
The DP8428 and DP8429 1M DRAM Controller Drivers are
designed to provide 鈥樷€楴o-Waitstate鈥欌€?CPU interface to Dy-
namic RAM arrays of up to 8 Mbytes and larger The
DP8428 and DP8429 are tailored for 32-bit and 16-bit sys-
tem requirements respectively Both devices are fabricated
using National鈥檚 new oxide isolated Advanced Low power
Schottky (ALS) process and use design techniques which
enable them to significantly out-perform all other LSI or dis-
crete alternatives in speed level of integration and power
consumption
Each device integrates the following critical 1M DRAM con-
troller functions on a single monolithic device ultra precise
delay line 9 bit refresh counter fall-through row column
and bank select input latches Row Column address mux-
ing logic on-board high capacitive-load RAS CAS Write
Enable and Address output drivers and precise control sig-
nal timing for all the above
In order to specify each device for 鈥樷€榯rue鈥欌€?worst case operat-
ing conditions all timing parameters are guaranteed while
the chip is driving the capacitive load of 88 DRAMs includ-
ing trace capacitance The chip鈥檚 delay timing logic makes
use of a patented new delay line technique which keeps AC
skew to
g
3 ns over the full V
CC
range of
g
10% and tem-
perature range of
b
55 C to
a
125 C The DP8428 and
DP8429 guarantee a maximum RASIN to CASOUT delay of
80 ns or 70 ns even while driving an 8 Mbyte memory array
with error correction check bits included Two speed select-
ed options of these devices are shown in the switching
characteristics section of this document
(Continued)
Features
Y
Y
Y
Y
Y
Y
Y
Y
Makes DRAM interface and refresh tasks appear virtu-
ally transparent to the CPU making DRAMs as easy to
use as static RAMs
Specifically designed to eliminate CPU wait states up to
10 MHz or beyond
Eliminates 20 discrete components for significant board
real estate reduction system power savings and the
elimination of chip-to-chip AC skewing
On-board ultra precise delay line
On-board high capacitive RAS CAS WE and Address
drivers (specified driving 88 DRAMs directly)
AC specified for directly addressing up to 8 Mbytes
Low power high speed bipolar oxide isolated process
Downward pin and function compatible with 256k
DRAM Controller Drivers DP8409A DP8417 DP8418
and DP8419
Contents
Y
Y
Y
Y
Y
Y
Y
System and Device Block Diagrams
Recommended Companion Components
Device Connection Diagrams and Pin Definitions
Device Differences DP8428 vs DP8429
Mode of Operation
(Descriptions and Timing Diagrams)
Application Description and Diagrams
DC AC Electrical Specifications Timing Diagrams and
Test Conditions
System Diagram
TL F 8649 鈥?1
TRI-STATE is a registered trademark of National Semiconductor Corp
PAL is a registered trademark of and used under license with Monolithic Memories Inc
C
1995 National Semiconductor Corporation
TL F 8649
RRD-B30M105 Printed in U S A

DP8429V-70相關(guān)型號PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！