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DP8421AV-25 Datasheet

  • DP8421AV-25

  • microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Dri...

  • 822.03KB

  • 58頁

  • NSC

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DP8420A 21A 22A microCMOS Programmable 256k 1M 4M Dynamic RAM Controller Drivers
July 1992
DP8420A 21A 22A microCMOS Programmable
256k 1M 4M Dynamic RAM Controller Drivers
General Description
The DP8420A 21A 22A dynamic RAM controllers provide a
low cost single chip interface between dynamic RAM and
all 8- 16- and 32-bit systems The DP8420A 21A 22A gen-
erate all the required access control signal timing for
DRAMs An on-chip refresh request clock is used to auto-
matically refresh the DRAM array Refreshes and accesses
are arbitrated on chip If necessary a WAIT or DTACK out-
put inserts wait states into system access cycles including
burst mode accesses RAS low time during refreshes and
RAS precharge time after refreshes and back to back ac-
cesses are guaranteed through the insertion of wait states
Separate on-chip precharge counters for each RAS output
can be used for memory interleaving to avoid delayed back
to back accesses because of precharge An additional fea-
ture of the DP8422A is two access ports to simplify dual
accessing Arbitration among these ports and refresh is
done on chip
of Pins
(PLCC)
68
68
84
of Address
Outputs
9
10
11
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
On chip high precision delay line to guarantee critical
DRAM access timing parameters
microCMOS process for low power
High capacitance drivers for RAS CAS WE and DRAM
address on chip
On chip support for nibble page and static column
DRAMs
Byte enable signals on chip allow byte writing in a word
size up to 32 bits with no external logic
Selection of controller speeds 20 MHz and 25 MHz
On board Port A Port B (DP8422A only) refresh arbitra-
tion logic
Direct interface to all major microprocessors (applica-
tion notes available)
4 RAS and 4 CAS drivers (the RAS and CAS configura-
tion is programmable)
Direct Drive
Memory
Capacity
4 Mbytes
16 Mbytes
64 Mbytes
Access
Ports
Available
Single Access Port
Single Access Port
Dual Access Ports (A and B)
Control
DP8420A
DP8421A
DP8422A
Largest
DRAM
Possible
256 kbit
1 Mbit
4 Mbit
Block Diagram
DP8420A 21A 22A DRAM Controller
TL F 8588 鈥?5
FIGURE 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
Staggered Refresh
TM
is a trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 8588
RRD-B30M105 Printed in U S A

DP8421AV-25 產(chǎn)品屬性

  • 18

  • 集成電路 (IC)

  • 存儲器 - 控制器

  • -

  • 動態(tài) RAM (DRAM)

  • 4.5 V ~ 5.5 V

  • 0°C ~ 70°C

  • 68-LCC（J 形引線）

  • 68-PLCC

  • 管件

  • *DP8421AV-25

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