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DP83952 Datasheet

  • DP83952

  • Repeater Interface Controller with Security Features (RIC II...

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  • NSC

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DP83952 Repeater Interface Controller with Security Features (RIC II)
PRELIMINARY
September 1995
DP83952
Repeater Interface Controller with
Security Features (RIC
TM
II)
General Description
The DP83952 RIC II Repeater Interface Controller is an
鈥樷€楨nhanced鈥欌€?version of the DP83950 RIC RIC II is fully
backward pin and functional compatible with the RIC The
DP83952 RIC II has the same basic architecture as the RIC
with additional feature enhancements RIC II provides addi-
tional network security options additional statistics for re-
peater activities and a faster processor interface When
RIC II is used in a 鈥樷€榥on-secure鈥欌€?mode it functions in the
same manner as the DP83950 RIC When RIC II is used in a
鈥樷€榮ecure鈥欌€?mode it restricts unauthorized nodes from intrud-
ing and or eavesdropping into the network The RIC II uti-
lizes internal CAMs to store compare addresses of valid
nodes when network security is desired
RIC II implements the IEEE 802 3 multiport repeater unit
specifications It is fully compliant with the 802 3 repeater
specification for the repeater segment partition and jabber
lockup protection state machines (Continued)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Separate Partition state machines for each port
Compatible with 802 3k Hub Management requirements
Provides port status information for LED displays in-
cluding receive collision partition link status and jab-
ber
Power-up configuration options
Repeater and Partition Specifications Transceiver Inter-
face Status Display Processor Operations
Simple processor interface for repeater management
and port disable
On-chip Event Counters and Event Flag Arrays
Serial Management Bus Interface to combine packet
and repeater status information
CMOS process for low power dissipation
Single 5V supply
Security Features
Y
Y
Features
Y
Y
Y
Y
Y
Y
Compliant with the IEEE 802 3 Repeater Specification
13 network connections (ports) per chip
Selectable on-chip twisted-pair transceivers
Cascadable for large hub applications
Compatible with AUI compliant transceivers
On-chip Elasticity Buffer Manchester encoder and
decoder
Y
Y
Power-up configuration options
Prevents unauthorized eavesdropping and or intrusion
on a per port basis
58 on-chip CAMs (Content Addressable Memory) allow
storage of acceptable addresses
Learn mode automatically records addresses of at-
tached nodes
1 0 System Diagram
TL F 12499 鈥?1
TRI-STATE is a registered trademark of National Semiconductor Corporation
RIC
TM
Inter-RIC
TM
and SONIC
TM
are trademarks of National Semiconductor Corporation
PAL is a registered trademark of and used under license from Advanced Micro Devices Inc
GAL is a registered trademark of Lattice Semiconductor
C
1995 National Semiconductor Corporation
TL F 12499
RRD-B30M115 Printed in U S A

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