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DP83936AVUL-20 Datasheet

  • DP83936AVUL-20

  • MHz Full Duplex SONIC-T Systems-Oriented Network Interface C...

  • 104頁

  • NSC

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DP83936AVUL-20 25 33 MHz Full Duplex SONIC-T Systems-Oriented
Network Interface Controller with Twisted Pair Interface
January 1996
DP83936AVUL-20 25 33 MHz Full Duplex SONIC
TM
-T
Systems-Oriented Network Interface Controller
with Twisted Pair Interface
General Description
The SONIC-T (Systems-Oriented Network Interface Control-
ler with Twisted Pair) is a second-generation Ethernet Con-
troller designed to meet the demands of today鈥檚 high-speed
32- and 16-bit systems Its system interface operates with a
high speed DMA that typically consumes less than 5% of
the bus bandwidth Selectable bus modes provide both big
and little endian byte ordering and a clean interface to stan-
dard microprocessors The linked-list buffer management
system of SONIC-T offers maximum flexibility in a variety of
environments from PC-oriented adapters to high-speed
motherboard designs The SONIC-T can be configured for
full duplex operation Furthermore the SONIC-T integrates
a fully-compatible IEEE 802 3 Encoder Decoder (ENDEC)
and a Twisted Pair Interface which provide a one-chip solu-
tion for Ethernet when using 10BASE-T When using
10BASE2 or 10BASE5 the SONIC-T may be paired with the
DP8392 Coaxial Transceiver Interface to achieve a simple
2-chip solution
For increased performance the SONIC-T implements a
unique buffer management scheme to efficiently process
receive and transmit packets in system memory No inter-
mediate packet copy is necessary The receive buffer man-
agement uses three areas in memory for (1) allocating addi-
tional resources (2) indicating status information and (3)
buffering packet data During reception the SONIC-T stores
packets in the buffer area then indicates receive status and
control information in the descriptor area The system allo-
cates more memory resources to the SONIC-T by adding
descriptors to the memory resource area The transmit buff-
er management uses two areas in memory
1 indicating status and control information
2 fetching packet data
The system can create a transmit queue allowing multiple
packets to be transmitted from a single transmit command
The packet data can reside on any arbitrary byte boundary
and can exist in several non-contiguous locations
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
32-bit non-multiplexed address and data bus
Configurable for Full Duplex operation
Auto AUI TPI selection
High-speed interruptible DMA
Linked-list buffer management maximizes flexibility
Two independent 32-byte transmit and receive FIFOs
Bus compatibility for all standard microprocessors
Supports big and little endian formats
Integrated IEEE 802 3 ENDEC
Integrated Twisted Pair Interface
Complete address filtering for up to 16 physical and or
multicast addresses
32-bit general-purpose timer
Loopback diagnostics
Fabricated in low-power CMOS
160 PQFP package
Full network management facilities support the 802 3
layer management standard
Integrated support for bridge and repeater applications
System Diagram
IEEE 802 3 Ethernet Thin-Ethernet 10BaseT Station
TL F 12597 鈥?1
TRI-STATE is a registered trademark of National Semiconductor Corporation
SONIC
TM
is a trademark of National Semiconductor Corporation
C
1996 National Semiconductor Corporation
TL F 12597
RRD-B30M36 Printed in U S A
http
www national com

DP83936AVUL-20 產(chǎn)品屬性

  • 24

  • 集成電路 (IC)

  • 接口 - 控制器

  • -

  • 網(wǎng)絡接口控制器（NIC）

  • 雙絞線

  • 4.75 V ~ 5.25 V

  • 140mA

  • 0°C ~ 70°C

  • 表面貼裝

  • 160-BQFP

  • 160-PQFP（28x28）

  • 管件

  • *DP83936AVUL-20

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