鈩?/div>
10/100/1000M
General Description
Features
The DP83891 is the 鏗乺st fully integrated, feature rich Physi-
s
Fully integrated 10BASE-T,100BASE-TX and
cal Layer transceiver with integrated PMD sublayers to sup-
1000BASE-T capable
port 10BASE-T,100BASE-TX and 1000BASE-T Ethernet
s
Single Quad TX-Transformer interface for all speeds
protocols. It operates on existing CAT5 cables which
s
Fully compliant to IEEE 802.3u 100BASE-TX and IEEE
reduces deployment costs.
802.3z/ab 1000BASE-T specifications. Fully integrated
The DP83891 is designed for easy implementation of
and fully compliant ANSI X3.T12 PMD physical sublayer
10/100/1000 Mb/s Ethernet LANs. It interfaces directly to
that includes adaptive equalization and Baseline Wan-
Twisted Pair media via an external standard Quad trans-
der compensation.
former. The DP83891 connects to the MAC layer through
s
Supports Auto-MDIX
the IEEE 802.3u Standard Media Independent Interface
(MII) or the IEEE 802.3z Gigabit Media Independent Inter-
s
IEEE 802.3u Auto-Negotiation and Parallel Detection
face (GMII).
鈥?Fully auto-negotiates between 10, 100 and 1000 Mb/s
full duplex and half duplex devices
Applications
s
3.3 V MAC interfaces:
鈥?IEEE 802.3u MII
The DP83891 鏗乼s applications in:
鈥?IEEE 802.3z GMII
s
10/100/1000 Mb/s capable node cards
s
LED support (Link, Speed, Activity, Duplex, Collision,
s
Switches with 10/100/1000 Mb/s capable ports
Auto-Negotiation, TX and RX indications)
s
High speed uplink ports (backbone)
s
Management Register Set (MDIO and MDC)
s
High end workstations
s
Single 3.3 V power supply
鈥?5 V tolerant I/Os
s
208-pin PQFP package
System Diagram
10/100/1000
ETHERNET
MAC
DP83891
10/100/1000 Mb/s
ETHERNET PHYSICAL LAYER
125 MH z
CLOCK
STATUS
LED s
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
漏
2000 National Semiconductor Corporation
Subject to change
MAGNETICS
MII/GMII
10BASE-T,
100BASE-TX or
1000BASE-T
10BASE-T,
100BASE-TX
or
RJ-45
1000BASE-T
www.national.com
Last Modi鏗乪d: 1/27/00
REVISION 0.0
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