Adaptive equalization and Baseline Wander comp.
鈻?/div>
IEEE 802.3u Auto-Negotiation and Parallel Detection
Ethernet protocols.
鈥?Fully auto-negotiates between 1000 Mb/s, 100 Mb/s,
The DP83864 contains four integrated ultra low power
and 10 Mb/s full duplex and half duplex devices
Gigabit Physical layers. It uses advanced 0.18
碌m,
1.8 V
CMOS technology, fabricated at National鈥檚 South Portland,
鈻?/div>
2.5 V/3.3 V MAC interfaces:
Maine facilities.
鈥?IEEE 802.3u MII with programmable bus ordering
鈥?IEEE 802.3z GMII with programmable bus ordering
The DP83864 is designed for easy implementation of
10/100/1000 Mb/s Ethernet LANs. Each port interfaces
鈥?Reduced GMII (RGMII) ver. 1.3
directly to Twisted Pair media via an external transformer.
鈥?Serial GMII (SGMII)
This device interfaces directly to the MAC layer through the
IEEE 802.3u Standard Media Independent Interface (MII)
鈻?/div>
LED support (Link10, Link100, Link1000, Activity and
Duplex indicators); Direct drive LED鈥檚 thru management
or the IEEE 802.3z Gigabit Media Independent Interface
(GMII). It also supports the reduced pin count RGMII (12
鈻?/div>
User Programmable Interrupt
pins per port) and serial GMII (8 pins per port).
鈻?/div>
A 25Mhz or 125Mhz oscillator as reference clock input
The DP83864 is a fourth generation of Gigabit Physical
鈻?/div>
PHY level CRC checking on received packets and PHY
layer product with field proven architecture and perfor-
level CRC generation for test mode transmit packets
mance. Its robust performance ensures drop in replace-
ment of existing 10/100M equipment with 10/100/1000M
鈻?/div>
292 BGA package
鈻?/div>
Power dissipation approximately 1 W / port
Networking infrastructure.
鈻?/div>
1.8 V CMOS (core & analog); 2.5 V (analog & I/O); 3.3 V
Applications
is optional for 3.3 V I/O voltage
The DP83864 fits applications in:
鈻?/div>
One management port per chip
鈻?/div>
Switches with 10/100/1000 Mb/s capable ports
鈻?/div>
Supports Auto-MDIX/polarity at all speeds
鈻?/div>
High speed uplink ports with redundancies (backbone)
鈻?/div>
One JTAG interface per chip
鈻?/div>
Servers with Quad Ethernet ports
System Diagram
MAGNETICS
RJ-45
RJ-45
RJ-45
RJ-45
Quad Port
10/100/1000 Mb/s
ETHERNET
MAC
DP83864
10/100/1000 Mb/s
ETHERNET
PHYSICAL LAYER
MAGNETICS
MII
GMII
RGMII
SGMII
25 MHz or
125 MHz
Oscillator
Status
LED鈥檚
Per Port
GigPHYTER
鈩?/div>
is a trademark of National Semiconductor Corporation.
MAGNETICS
MAGNETICS
10BASE-T,
100BASE-TX,
or
1000BASE-T
漏
2003 National Semiconductor Corporation
www.national.com
DP83864AUT相關(guān)型號PDF文件下載
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型號
版本
描述
廠商
下載
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英文版
Single 8-bit Bus Transceiver
ETC
-
英文版
Single 8-bit Bus Transceiver
-
英文版
Single 8-bit Bus Transceiver
ETC
-
英文版
Single 8-bit Bus Transceiver
-
英文版
Single 8-bit Bus Transceiver
ETC
-
英文版
Single 8-bit Bus Transceiver
-
英文版
Single 8-bit Bus Transceiver
ETC
-
英文版
Single 8-bit Bus Transceiver
-
英文版
8-Bit TRI-STATE Bidirectional Transceiver (Non-Inverting)
NSC
-
英文版
8-Bit TRI-STATE Bidirectional Transceiver (Non-Inverting)
NSC [Natio...
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英文版
Octal Latched Peripheral Drivers
NSC
-
英文版
DP7310/DP8310/DP7311/DP8311 Octal Latched Peri...
NSC [Natio...
-
英文版
Octal Latched Peripheral Drivers
NSC [Natio...
-
英文版
Octal Latched Peripheral Drivers
NSC
-
英文版
DP7310/DP8310/DP7311/DP8311 Octal Latched Peri...
NSC [Natio...
-
英文版
Octal Latched Peripheral Drivers
NSC [Natio...
-
英文版
Biphase Communications ProcessorぱBCP
NSC
-
英文版
Biphase Communications ProcessorぱBCP
NSC [Natio...
-
英文版
NIC Network Interface Controller
NSC
-
英文版
NIC Network Interface Controller
NSC [Natio...
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