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DP83856B Datasheet

  • DP83856B

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DP83856B 100 Mb/s Repeater Information Base
PRELIMINARY
N
Information Base
DP83856B 100 Mb/s Repeater
General Description
The DP83856B 100 Mb/s Repeater Information
Base is designed specifically to meet the
management demands of today's high speed
Ethernet networking systems.
The DP83856B simplifies design of managed
multiport repeaters. Used in conjunction with up to
16 DP83850s it enables a repeater system to
become a single managed entity that is fully
compatible with the IEEE 802.3u clause 30
management requirements.
The DP83856B device incorporates all the
necessary functions and counters for collecting
network statistics. Information is gathered on a
per-packet, per-port basis: the port which is
receiving the packet is the active port for statistics
collection.
October 1997
Features
鈥?Supports up to 16 DP83850 Repeater Interface
Controllers (192, 100Mb ports on one segment)
鈥?Fully IEEE 802.3u clause 30 compatible
鈥?Network management statistics processed on a
per activity (per packet) basis
鈥?Programmed I/O interface for statistics reporting
鈥?Uses external SRAM to maintain per port
network management statistics counters
鈥?Single interrupt acknowledgment provides
report on all per port SRAM based and P83856B
based statistics
鈥?Parallel register interface to CPU (16-bit)
鈥?Allows indirect access to the DP83850
Repeater Interface Controller and DP83840
Physical Layer Device serial registers through a
parallel register interface
鈥?132 pin PQFP
System Diagram
Man agement
CPU
Management
Memory/Cod e
CPU Bus
Management
I/O Device/s
DP83856B
100 Mb/s
Repeater Information Base
Statistics
SRAM
Inter Repeater Bus, TX Bus and
Seri al Management Bus Si gnals
DP83850 100 Mb/s Repeater
Interface Controller
100 Mb/s
PHY #1
100 Mb/s
PHY #2
100 Mb/s
PHY #12
DP83850 100 Mb/s Repeater
In terface Controller
100 Mb/s
P HY #13
100 Mb/s
PHY #14
100 Mb/s
PHY #24
TRI-STATE廬 is a registered trademark of National Semiconductor corporation.
漏1997
National Semiconductor Corportation
www.national.com

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