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DP83850C Datasheet

  • DP83850C

  • 100 Mb/s TX/T4 Repeater Interface Controller (100RIC⑩)

  • 37頁(yè)

  • NSC

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DP83850C 100 Mb/s TX/T4 Repeater Interface Controller (100RIC鈩?
June 1998
DP83850C 100 Mb/s TX/T4 Repeater Interface Controller
(100RIC
鈩?/div>
)
General Description
Features
The DP83850C 100 Mb/s TX/T4 Repeater Interface Con-
s
IEEE 802.3u repeater and management compatible
troller, known as 100RIC, is designed speci鏗乧ally to meet
s
Supports Class II TX translational repeater and Class I
the needs of today's high speed Ethernet networking sys-
T4 repeater
tems. The DP83850C is fully compatible with the IEEE
s
Supports 12 network connections (ports)
802.3 repeater's clause 27.
s
Up to 31 repeater chips cascadable for larger hub appli-
The DP83850C supports up to twelve 100 Mb/s links with
cations (up to 372 ports)
its network interface ports. The 100RIC can be con鏗乬ured
to be used with either 100BASE-TX or 100BASE-T4 PHY
s
Separate jabber and partition state machines for each
port
technologies. Larger repeaters with up to 372 ports may
be constructed by cascading DP83850Cs together using
s
Management interface to DP83856 allows all repeater
the built-in Inter Repeater bus.
MIBs to be maintained
In conjunction with a DP83856 100 Mb/s Repeater Infor-
s
Large per-port management counters - reduces man-
agement CPU overhead
mation Base device, a DP83850C based repeater
becomes a managed entity that is compatible with IEEE
s
On-chip elasticity buffer for PHY signal re-timing to the
802.3u (clause 30), collecting and providing an easy inter-
DP83850C clock source
face to all the required network statistics.
s
Serial register interface - reduces cost
s
Physical layer device control/status access available via
the serial register interface
s
Detects repeater identification errors
s
132 pin PQFP package
System Diagram
DP83850C
100 Mb/s
Repeater Interface Controller
(100RIC8)
Inter Repeater Bus
Management Bus
RX Enable [11..0]
MII
DP83840A
100 PHY
#0
DP83223
100BASE-X
Transceiver
Port 0
DP83840A
100 PHY
#1
DP83223
100BASE-X
Transceiver
Port 1
DP83840A
100 PHY
#2
DP83223
100BASE-X
Transceiver
Port 2
DP83840A
100 PHY
#11
DP83223
100BASE-X
Transceiver
Port 11
DP83856
100 Mb/s
Repeater Information Base
(100RIB)
(TXD[3:0], TX_ER, TX_RDY)
(IR_COL, IR_DV)
Statistics
SRAM
Management
CPU
Program
Memory
100Mb/s
Ethernet
Ports
Management
I/O Devices
Note: The above system diagram depicts the repeater con鏗乬ured in 100BASE-TX mode.
FAST
廬
is a registered trademark of Fairchild Semiconductor Corporation.
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
100RIC
鈩?/div>
is a trademark of National Semiconductor Corporation.
漏
1998 National Semiconductor Corporation
www.national.com

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