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DP83291EB Datasheet

  • DP83291EB

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DP83291EB FDDI MAC Layer Evaluation Board
April 1990
DP83291EB
FDDI MAC Layer Evaluation Board
General Description
The DP83291EB FDDI MAC Layer Evaluation Board is a
PC-AT compatible board that implements the MAC Layer
functions of the FDDI standard The Board utilizes the Na-
tional Semiconductor DP83261 BMAC
TM
device along with
PAL -based Buffer Management Logic to implement a sim-
ple MAC Layer
The MAC Demonstration Board features two 8k x 8 buffers
that are configured as Dual Ported Memory One memory
bank is dedicated to receive while the other is dedicated to
transmit This configuration supports full duplex transmis-
sion to self
The MAC board contains expansion connectors to interface
to the Link Card Three busses are provided two for data
paths and one for clock paths The MAC Card is used with a
single Link Card to implement a Single Attach Station (SAS)
and two Link Cards to implement a Dual Attach Station
(DAS)
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
PC-AT compatible full size card
Dual ported memory interface full duplex data path
Interfaces to link cards for DAS or SAS configurations
Supported by demonstration software
Utilizes DP83261 BMAC device
Full network statistics
Supports asynchronous and synchronous transmission
classes
Supports confirmation services
PAL based buffer management
Table of Contents
1 0 General Description
2 0 Address Mapping
3 0 Installation
4 0 Board Register Description
5 0 Memory Interface
6 0 Frame Transmission
7 0 Frame Reception
8 0 Software Interface
9 0 Implementation Notes
Appendix
TL F 10824 鈥?1
FIGURE 1 DP83291EB Block Diagram Overview
BMAC
TM
CDD
TM
and PLAYER
TM
are trademarks of National Semiconductor Corporation
PAL is a registered trademark of and used under license from Advanced Micro Devices Inc
IBM PC and PC-AT are registered trademarks of International Business Machines Corporation
C
1995 National Semiconductor Corporation
TL F 10824
RRD-B30M105 Printed in U S A

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