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DP83222 Datasheet

  • DP83222

  • 12頁(yè)

  • ETC

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DP83222 CYCLONE Twisted Pair FDDI Stream Cipher Device
August 1994
DP83222
CYCLONE
TM
Twisted Pair FDDI Stream Cipher Device
General Description
The DP83222 CYCLONE Stream Cipher Scrambler
Descrambler Device is an integrated circuit designed to in-
terface directly with the serial bit streams of a Twisted Pair
FDDI PMD The DP83222 is designed to be fully compatible
with the National Semiconductor FDDI Chip Sets including
the DP83223 TWISTER
TM
(Twisted Pair Transceiver) The
DP83222 requires a 125 MHz Transmit Clock and corre-
sponding Receive Clock for synchronous data scrambling
and descrambling The DP83222 is compliant with the ANSI
X3T9 5 TP-PMD draft standard and is required for the re-
duction of EMI emission over unshielded media The
DP83222 is specified to work in conjunction with existing
twisted pair transceiver signalling schemes such as MLT-3
or NRZI and enables high bandwidth transmission over
Twisted Pair copper media
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Enables 100 Mbps FDDI signalling over Category 5
Unshielded Twisted Pair (UTP) cable and Type 1
Shielded Twisted Pair (STP)
Reduces EMI emissions over Twisted Pair media
Compatible with ANSI X3T9 5 TP-PMD Standard
Requires a single
a
5V supply
Transparent mode of operation
Flexible NRZ and NRZI format options
Advanced BiCMOS process
Signal Detect and Clock Detect inputs provided for en-
hanced functionality
Suitable for Fiber Optic PMD replacement applications
Block Diagram
TL F 11885 鈥?1
FIGURE 1 DP83222 Block Diagram
CYCLONE
TM
CDD
TM
CDL
TM
PLAYER
TM
PLAYER
a
TM
and TWISTER
TM
are trademarks of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 11885
RRD-B30M105 Printed in U S A

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