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DP3S1MX32PY5-10CI Datasheet

  • DP3S1MX32PY5-10CI

  • x32 SRAM Module

  • 511.94KB

  • 6頁

  • ETC

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2Mx8/1Mx16/512Kx32,
30A244-00
A
12 - 20ns, Surface Mount
32 Megabit CMOS SRAM
DP3S1MX32PY5
ADVANCED INFORMATION
PIN-OUT DIAGRAM
DESCRIPTION:
The DP3S1MX32PY5 is a 1M x 32 SRAM module
that utilizes the new and innovative space saving
TSOP stacking technology. The module is
constructed of two 1M x 16 SRAM鈥?that are
s
configured as a 1M x 32.
The DP3S1MX32PY5 module features high speed
access times with common data inputs and outputs.
FEATURES:
鈥?/div>
Organizations Available: 1M x 32
鈥?/div>
Access Times: 10*, 12, 15, 20ns
鈥?/div>
3.3
鹵
0.3** Volt Power Requirement
鈥?/div>
Fully Static Operation - No clock or refresh
required
鈥?/div>
TTL-compatible Inputs and Outputs
鈥?/div>
80-Pin Surface Mount LP-Stack 鈩?/div>
PIN NAMES
A0 - A19
I/O0 - I/O31
CS
WE
OE
BS0
BS1
BS2
BS3
V
DD
V
SS
NU.
Address Inputs
Data Input/Output
Stack Enable
Write Enable
Output Enable
Byte Select I/O0 - I/O7
Byte Select I/O8 - I/O15
Byte Select I/O16 - I/O23
Byte Select I/O24 - I/O31
Power (+3.3V)
Ground
Not Usable
FUNCTIONAL BLOCK DIAGRAM
* 0擄-70擄 only.
** 5% for 10ns only.
30A244-00
REV. A
This document contains information on a product under consideration for
development at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right to
change or discontinue information on this product without prior notice.
1
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