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DO-DI-PCI64-IP Datasheet

  • DO-DI-PCI64-IP

  • Controller Miscellaneous - Datasheet Reference

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  • 5頁

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LogiCORE PCI64 Interface v3.0
Interface Data Sheet
December 14, 2001
Data Sheet, v3.0.090
LogiCORE Facts
PCI64 Resource Utilization
1
Slice Four Input LUTs
724
Slice Flip Flops
732
IOB Flip Flops
176
IOBs
89
TBUFs
352
GCLKs
1
2
Provided with Core
Documentation
PCI Design Guide
PCI Implementation Guide
Design File Formats
Verilog/VHDL Simulation Model
NGO Netlist
Constraint Files
User Constraint Files (UCF)
Guide Files (NCD)
Example Design
Verilog/VHDL Example Design
Design Tool Requirements
Xilinx Tools
v4.1i SP3
Tested Entry and
Synplicity Synplify
Verification Tools
3
Synopsys FPGA Express
Exemplar Leonardo Spectrum
Cadence Verilog XL
Model Technology ModelSim
Xilinx provides technical support for this LogiCORE product when
used as described in the Design Guide and the Implementation
Guide. Xilinx cannot guarantee timing, functionality, or support of
product if implemented in devices not listed, or if customized be-
yond that allowed in the product documentation.
1. The resource utilization depends on configuration of the inter-
face and the user design. Unused resources are trimmed by the
Xilinx technology mapper. The utilization figures reported in this
table are representative of a maximum configuration.
2. Designs running at 66 MHz in devices other than Virtex-II require
one GCLKIOB and two GCLKs.
3. See the implementation guide or product release notes for cur-
rent supported versions.
Xilinx Inc.
2100 Logic Drive
San Jose, CA 95124
Phone: +1 408-559-7778
Fax:
+1 408-559-7114
URL:
www.xilinx.com/ipcenter
Support: www.support.xilinx.com
Introduction
With the Xilinx LogiCORE PCI Interface, a designer can
build a customized, fully PCI 2.2 compliant system with the
highest possible sustained performance, 528 Mbytes/sec.
Features
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Fully PCI 2.2 compliant, 64/32-bit, 66/33 MHz interface.
Customizable, programmable, single-chip solution.
Pre-defined implementation for predictable timing.
Incorporates Xilinx Smart-IP Technology.
3.3 V operation at 0-66 MHz.
5.0 V operation at 0-33 MHz
Fully verified design tested with Xilinx proprietary
testbench and hardware.
Available for configuration and download on the web:
- Web-based Configuration and Download Tool
- Web-based User Constraint File Generator Tool
CardBus Compliant
Supported initiator functions:
- Configuration Read, Configuration Write
- Memory Read, Memory Write, MRM, MRL
- Interrupt Acknowledge, Special Cycles
- I/O Read, I/O Write
Supported target functions:
- Type 0 Configuration Space Header
- Up to 3 Base Address Registers (MEM or I/O with
adjustable block size from 16 bytes to 2 Gbytes)
- Medium Decode Speed
- Parity Generation, Parity Error Detection
- Configuration Read, Configuration Write
- Memory Read, Memory Write, MRM, MRL
- Interrupt Acknowledge
- I/O Read, I/O Write
- Target Abort, Target Retry, Target Disconnect
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December 14, 2001
1

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