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DO-DI-10GEMAC Datasheet

  • DO-DI-10GEMAC

  • Controller Miscellaneous - Datasheet Reference

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10-Gigabit Ethernet MAC
with XGMII or XAUI v2.1
DS201 (v2.1) June 24, 2002
0
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Product Specification
LogiCORE鈩?Facts
Features
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Single-speed full-duplex 10-gigabits-per-second
Ethernet Media Access Controller
Designed to Draft D4.1 of IEEE P802.3ae specification
Choice of XGMII or XAUI interface to PHY layer
Uses Virtex鈩?II DDR I/O primitives for the optional
XGMII interface
Uses Virtex-II Pro鈩?Multi Gigabit Transceivers for the
optional XAUI interface
Cut-through operation with minimum buffering for
maximum flexibility in 64-bit client bus interfacing
Configured and monitored through an independent
microprocessor-neutral interface
Uses Virtex-II/Virtex-II Pro Digital Clock Management
to implement XGMII and XAUI interface timing
Powerful statistics gathering to internal counters.
Statistics vectors are also output to the user.
Configurable flow control through MAC Control pause
frames; symmetrically or asymmetrically enabled
New-style Clause 45 MDIO interface to managed
objects in PHY layers
Supports LAN/WAN (OC-192c data rate) functionality
through open loop rate control
Configurable support of VLAN frames to specification
IEEE 802.3-2000
Configurable support of 鈥渏umbo frames鈥?of any length
Configurable interframe gap length adjustment
Remote Fault/Local Fault signalling at the
Reconciliation Sublayer
Available under terms of the SignOnce IP License
Documentation
Design File Formats
Constraints File
Size
Global Clock Buffers
Special Features
Performance
Supported Families
Speed Grades
Core Specifics
Virtex-II, Virtex-II Pro
-5 speed grade on Virtex-II
(XGMII version only)
-7 speed grade on Virtex-II Pro
156.25 MHz internal clock;
156.25MHz DDR on
XGMII interface;
3.125Gbps per lane on XAUI
interface
3000-4400 slices
3
Digital Clock Management
integrated into core
Provided with Core
Product Specification
EDIF netlist
.ucf
Design Tools Requirements
Xilinx Core Tools v4.2i SP2
Support
Support provided by Xilinx
TCP
IP
FIFO
I/F
MAC
PCS
WIS
PMA
PMD
XIP2092
Figure 1:
Typical 10-Gigabit Ethernet Architecture
漏 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other
trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,
application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may
require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties
or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
DS201 (v2.1) June 24, 2002
Product Specification
www.xilinx.com
1-800-255-7778
1

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