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Advance Data Sheet

March 2000

DNC5X3125

Gigabit Ethernet Transceiver Macrocell

Overview

The DNC5X3125 is a low-cost, low-power transceiver

macrocell. It is used for data transmission over fiber

or coaxial media in conformance with

IEEE*

802.3z

Gigabit Ethernet specification and Fibre Channel

ANSI

鈥?/div>

X3T11 at 1.0 Gbits/s and 1.25 Gbits/s.

The transmitter section accepts parallel 10-bit

8b/10b encoded data that is latched on the rising

edge of TBC. It also accepts the low-speed, TTL

compatible system clock, REFCLK, and uses this

clock to synthesize the internal high-speed serial bit

clock. The serialized data is then available at the dif-

ferential PECL outputs, terminated in 50

鈩?/div>

or 75

鈩?/div>

to

drive either an optical transmitter or coaxial media.

The receive section receives high-speed serial data

at its differential PECL input port. This data is fed to

the digital clock recovery section, which generates a

recovered clock and retimes the data. The retimed

data is deserialized and presented as 10-bit parallel

data on the output port. A divided-down version of

the recovered clock, synchronous with parallel data

bytes, is also available as a TTL compatible output.

The receive section recognizes the comma character

and aligns the comma-containing byte on the word

boundary, when ENCDET = 1.

Features

s

Designed to operate in Ethernet, fibre channel,

FireWire

鈥?/div>

or backplane applications.

Operationally compliant to

IEEE

802.3z Gigabit

Ethernet specification.

Operationally compliant to Fibre Channel

ANSI

X3T11. Provides FC-0 services at 1.0 Gbits/s鈥?/div>

1.25 Gbits/s (10-bit encoded data rate).

100 MHz鈥?25 MHz differential or single-ended

reference clock.

10-bit parallel interface.

8b/10b encoded data.

High-speed comma character recognition (K28.1,

K28.5, K28.7) for latency-sensitive applications

and alignment to word boundary.

Two 50.0 MHz鈥?2.5 MHz receive-byte clocks.

Single analog PLL design requires no external

components for the frequency synthesizer.

Novel digital data lock in receiver avoids the need

for multiple analog PLLs.

Expandable beyond single-channel SERDES.

PECL high-speed interface I/O for use with optical

transceiver or coaxial copper media.

Requires one external resistor for PECL output ref-

erence level definition.

Low-power digital 0.25 碌m CMOS technology.

3.3 V 鹵 5% power supply.

0 擄C鈥?0 擄C ambient temperature.

s

*

IEEE

is a registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

鈥?/div>

ANSI

is a registered trademark of American National Standards

Institute.

鈥?/div>

FireWire

is a registered trademark of Apple Computer, Inc.

型號

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DNC5X3125

英文版

Gigabit Ethernet Transceiver Macrocell

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DNC5X3125

英文版

Gigabit Ethernet Transceiver Macrocell

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