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DMN2005DLP4K-7 Datasheet

  • DMN2005DLP4K-7

  • DUAL N-CHANNEL ENHANCEMENT MODE FIELD EFFECT TRANSISTOR

  • 4頁(yè)

  • DIODES

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上傳產(chǎn)品規(guī)格書

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SPICE MODEL: DMN2005DLP4K
DMN2005DLP4K
DUAL N-CHANNEL ENHANCEMENT MODE FIELD EFFECT TRANSISTOR
NEW PRODUCT
Features
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Low On-Resistance
Very Low Gate Threshold Voltage, 0.9V Max.
Fast Switching Speed
Low Input/Output Leakage
Ultra-Small Surface Mount Package
Lead Free By Design/RoHS Compliant (Note 2)
"Green" Device (Note 4)
ESD Protected Gate
Ultra Low Profile Package
D
1
G
2
S
2
Dim
A
B
C
DFN1310H4-6
Min
1.25
0.95
0.20
-
-
-
0
0.10
0.30
-
-
-
Max
1.38
1.08
0.30
-
-
0.40
0.05
0.20
0.50
-
-
-
Typ
1.30
1.00
0.25
0.10
0.20
-
0.20
0.15
0.40
0.35
0.25
0.05
S
1
G
1
D
2
D*
E**
G
H
Top View
G
H
Mechanical Data
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Case: DFN1310H4-6
Case Material: Molded Plastic, 鈥淕reen鈥?Molding
Compound. UL Flammability Classification Rating
94V-0
Moisture Sensitivity: Level 1 per J-STD-020C
Terminal Connections: See Diagram
Terminals: Finish
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NiPdAu annealed over Copper
leadframe. Solderable per MIL-STD-202, Method 208
Marking: See Page 4
Ordering & Date Code Information: See Page 4
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Side View
Z
01
K*
L*
M**
N*
Z**
K
L
E
N
C
B
All Dimensions in mm
* Dimensions D, K, L, N Repeat 4X
** Dimensions E, M, Z Repeat 2X
D
D
N
A
M
Z
Bottom View
ESD protected
Maximum Ratings
Drain-Source Voltage
@T
A
= 25擄C unless otherwise specified
Symbol
V
DSS
V
GSS
Continuous
Pulsed (Note 3)
I
D
P
d
R
胃JA
T
j
, T
STG
Value
20
鹵10
200
250
350
357
-65 to +150
Unit
V
V
mA
mW
擄C/W
擄C
Characteristic
Gate-Source Voltage
Drain Current per element (Note 1)
Total Power Dissipation (Note 1)
Thermal Resistance, Junction to Ambient
Operating and Storage Temperature Range
Notes:
1.
2.
3.
4.
Device mounted on FR-4 PCB.
No purposefully added lead.
Pulse width
鈮?0渭S,
Duty Cycle
鈮?%.
Diodes Inc.'s "Green" policy can be found on our website at http://www.diodes.com/products/lead_free/index.php.
DS30801 Rev. 6 - 2
1 of 4
www.diodes.com
DMN2005DLP4K
漏 Diodes Incorporated

DMN2005DLP4K-7 產(chǎn)品屬性

  • 3,000

  • 分離式半導(dǎo)體產(chǎn)品

  • FET - 陣列

  • -

  • 2 個(gè) N 溝道（雙）

  • 邏輯電平門

  • 20V

  • 200mA

  • 1.5 歐姆 @ 10mA，4V

  • 900mV @ 100µA

  • -

  • -

  • 350mW

  • 表面貼裝

  • 6-SMD，無(wú)引線

  • 6-DFN1310H4（1.0x1.3）

  • 帶卷 (TR)

  • DMN2005DLP4KDITR

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