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DM81LS95AWM Datasheet

  • DM81LS95AWM

  • 3-STATE Octal Buffer

  • 7頁

  • FAIRCHILD

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DM81LS95A 鈥?DM81LS96A 鈥?DM81LS97A 3-STATE Octal Buffer
September 1991
Revised May 1999
DM81LS95A 鈥?DM81LS96A 鈥?DM81LS97A
3-STATE Octal Buffer
General Description
These devices provide eight, two-input buffers in each
package. All employ low-power-Schottky TTL technology.
One of the two inputs to each buffer is used as a control
line to gate the output into the high-impedance state, while
the other input passes the data through the buffer. The
DM81LS95A and DM81LS97A present true data at the out-
puts, while the DM81LS96A is inverting. On the
DM81LS95A and DM81LS96A versions, all eight 3-STATE
enable lines are common, with access through a 2-input
NOR gate. On the DM81LS97A version, four buffers are
enabled from one common line, and the other four buffers
are enabled form another common line. In all cases the
outputs are placed in the 3-STATE condition by applying a
high logic level to the enable pins.
Features
s
Typical power dissipation
DM81LS95A, DM81LS97A
DM81LS96A
s
Typical propagation delay
DM81LS95A, DM81LS97A
DM81LS96A
15 ns
10 ns
80 mW
65 mW
s
Low power-Schottky, 3-STATE technology
Ordering Code:
Order Number
DM81LS95AWM
DM81LS95AN
DM81LS96AWM
DM81LS96AN
DM81LS97AN
Package Number
M20B
N20A
M20B
N20A
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Pin Descriptions
DM81LS95A and DM92LS96A
Pin Names
A1鈥揂8
Y1鈥揧8
G1鈥揋2
Inputs
Outputs
Active LOW Output Enables (Note 1)
Descriptions
Note 1:
Both G1 and G2 must be LOW for outputs to be enabled.
DM81LS97A
Pin Names
A1鈥揂8
Y1鈥揧8
G1
G2
Inputs
Outputs
Active LOW Output Enable (Y1鈥揧4)
Active LOW Output Enable (Y5鈥揧8)
Descriptions
漏 1999 Fairchild Semiconductor Corporation
DS006435
www.fairchildsemi.com

DM81LS95AWM 產(chǎn)品屬性

  • Fairchild Semiconductor

  • 8

  • 8

  • Non-Inverting

  • 5.25 V

  • 4.75 V

  • + 70 C

  • SMD/SMT

  • SOIC-20 Wide

  • - 5.2 mA

  • LS

  • Bipolar

  • 24 mA

  • 0 C

  • 8

  • 3-State

  • 40 ns at 5 V

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