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DM74S257N Datasheet

  • DM74S257N

  • 3-STATE Quad 1-of-2 Data Selector/Multiplexer

  • 5頁

  • FAIRCHILD

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DM74S257 3-STATE Quad 1-of-2 Data Selector/Multiplexer
August 1986
Revised May 2000
DM74S257
3-STATE Quad 1-of-2 Data Selector/Multiplexer
General Description
These Schottky-clamped high-performance multiplexers
feature 3-STATE outputs that can interface directly with
data lines of bus-organized systems. With all but one of the
common outputs disabled (at a high impedance state), the
low impedance of the single enabled output will drive the
bus line to a HIGH or LOW logic level. To minimize the pos-
sibility that two outputs will attempt to take a common bus
to opposite logic levels, the output enable circuitry is
designed such that the output disable times are shorter
than the output enable times.
This 3-STATE output feature means that n-bit (paralleled)
data selectors with up to 258 sources can be implemented
for data buses. It also permits the use of standard TTL reg-
isters for data retention throughout the system.
Features
s
3-STATE versions S157, S158, with same pin-outs
s
Schottky-clamped for significant improvement in
A-C performance
s
Provides bus interface from multiple sources in high-per-
formance systems
s
Average propagation delay from data input
s
Typical power dissipation
4.8 ns
320 mW
Ordering Code:
Order Number
DM74S257N
Package Number
N16E
Package Description
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Function Table
Inputs
Output
Control
H
L
L
L
L
H
=
HIGH Level
L
=
LOW Level
X
=
Don鈥檛 Care
Z
=
High Impedance (OFF)
Output
A
X
L
H
X
X
B
X
X
X
L
H
Y
Z
L
H
L
H
Select
X
L
L
H
H
漏 2000 Fairchild Semiconductor Corporation
DS006482
www.fairchildsemi.com

DM74S257N 產(chǎn)品屬性

  • Fairchild Semiconductor

  • Multiplexer

  • S

  • 8 / 4

  • 11 ns at 5 V

  • 5.25 V

  • 4.75 V

  • + 70 C

  • Through Hole

  • PDIP-16

  • Rail

  • 0 C

  • 8

  • 4

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