DM74S253 Dual 3-STATE 1-of-4 Line Data Selector/Multiplexer
August 1986
Revised May 2000
DM74S253
Dual 3-STATE 1-of-4 Line Data Selector/Multiplexer
General Description
Each of these Schottky-clamped data selectors/multiplex-
ers contains inverters and drivers to supply fully comple-
mentary, on-chip, binary decoding data selection to the
AND-OR gates. Separate output control inputs are pro-
vided for each of the two four-line sections.
The 3-STATE outputs can interface directly with data lines
of bus-organized systems. With all but one of the common
outputs disabled (at a high impedance state), the low
impedance of the single enable output will drive the bus
line to a HIGH or LOW logic level.
Features
s
3-STATE version of S153 with same pin-out
s
Schottky-diode-clamped transistors
s
Permits multiplexing from N lines to 1 line
s
Performs parallel-T-serial conversion
s
Strobe/output control
s
High fan-out totem-pole outputs
s
Typical propagation delay
From data to output
From select to output
6 ns
12 ns
s
Typical power dissipation 275 mW
Ordering Code:
Order Number
DM74S253N
Package Number
N16E
Package Description
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Function Table
Select
Inputs
B
X
L
L
L
L
H
H
H
H
A
X
L
L
H
H
L
L
H
H
C0
X
L
H
X
X
X
X
X
X
C1
X
X
X
L
H
X
X
X
X
C2
X
X
X
X
X
L
H
X
X
C3
X
X
X
X
X
X
X
L
H
Data Inputs
Output
Control
G
H
L
L
L
L
L
L
L
L
Y
Z
L
H
L
H
L
H
L
H
Output
Address inputs A and B are common to both sections.
H
=
HIGH Level
L
=
LOW Level
X
=
Don鈥檛 Care
Z
=
High Impedance
漏 2000 Fairchild Semiconductor Corporation
DS006481
www.fairchildsemi.com
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