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DM74S174N Datasheet

  • DM74S174N

  • Hex/Quad D Flip-Flop with Clear

  • FAIRCHILD

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DM74S174 鈥?DM74S175 Hex/Quad D Flip-Flop with Clear
August 1986
Revised April 2000
DM74S174 鈥?DM74S175
Hex/Quad D Flip-Flop with Clear
General Description
These positive-edge-triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic. All have a direct clear
input, and the quad (DM74S175) versions feature comple-
mentary outputs from each flip-flop.
Information at the D inputs meeting the setup time require-
ments is transferred to the Q outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a partic-
ular voltage level and is not directly related to the transition
time of the positive-going pulse. When the clock input is at
either the HIGH or LOW level, the D input signal has no
effect at the output.
Features
s
DM74S174 contain six flip-flops with single-rail outputs.
s
DM74S175 contain four flip-flops with double-rail out-
puts.
s
Buffered clock and direct clear inputs
s
Individual data input to each flip-flop
s
Applications include:
Buffer/storage registers
Shift registers
Pattern generators
s
Typical clock frequency 110 MHz
s
Typical power dissipation per flip-flop 75mW
Ordering Code:
Order Number
DM74S174N
DM74S175N
Package Number
N16E
N16E
Package Description
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagrams
DM74S174
DM74S175
漏 2000 Fairchild Semiconductor Corporation
DS006472
www.fairchildsemi.com

DM74S174N 產(chǎn)品屬性

  • Fairchild Semiconductor

  • 7, 4

  • DM74

  • D-Type Flip-Flop

  • Non-Inverting

  • Single-Ended

  • Single-Ended

  • 21 ns

  • - 1 mA

  • 20 mA

  • 5.25 V

  • + 70 C

  • Through Hole

  • PDIP-16

  • Rail

  • 0 C

  • 6

  • 6

  • 4.75 V

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