DM54LS502 DM74LS502 8-Bit Successive Approximation Register
April 1992
DM54LS502 DM74LS502
8-Bit Successive Approximation Register
General Description
The LS502 is an 8-bit register with the interstage logic nec-
essary to perform serial-to-parallel conversion and provide
an active LOW Conversion Complete (CC) signal coincident
with storage of the eighth bit An active LOW Start (S) input
performs synchronous initialization which forces Q7 LOW
and all other outputs HIGH Subsequent clocks shift this Q7
LOW signal downstream which simultaneously backfills the
register such that the first serial data (D input) bit is stored in
Q7 the second bit in Q6 the third in Q5 etc The serial
input data is also synchronized by an auxiliary flip-flop and
brought out on Q
D
Designed primarily for use in the successive approximation
technique for analog-to-digital conversion the LS502 can
also be used as a serial-to-parallel converter ring counter
and as the storage and control element in recursive digital
routines
Features
Y
Y
Y
Low power Schottky version of 2502
Storage and control for successive approximation A to
D conversion
Performs serial-to-parallel conversion
Connection Diagram
Dual-In-Line Package
Logic Symbol
TL F 10189 鈥?2
V
CC
e
Pin 16
GND
e
Pin 8
TL F 10189 鈥?1
Order Number DM54LS502J DM54LS502W
DM74LS502WM or DM74LS502N
See NS Package Number J16A M16B N16E or W16A
Pin
Names
D
S
CP
Q
D
CC
Q0鈥換7
Q7
Description
Serial Data Input
Start Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Synchronized Serial Data Output
Conversion Complete Output (Active LOW)
Parallel Register Outputs
Complement of Q7 Output
C
1995 National Semiconductor Corporation
TL F 10189
RRD-B30M105 Printed in U S A
1
2
3
4
5
6
