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DM74LS469 Datasheet

  • DM74LS469

  • 8-Bit Up/Down Counter

  • 162.05KB

  • FAIRCHILD

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DM74LS469 8-Bit Up/Down Counter
April 1998
DM74LS469
8-Bit Up/Down Counter
General Description
The 鈥橪S469 is an 8-bit synchronous up/down counter with
parallel load and hold capability. Three function-select inputs
(LD, UD, CBI) provide one of four operations which occur
synchronously on the rising edge of the clock (CK).
The LOAD operation loads the inputs (D
7
鈥揇
0
) into the output
register (Q
7
鈥換
0
). The HOLD operation holds the previous
value regardless of clock transitions. The INCREMENT op-
eration adds one to the output register when the carry-in in-
put is TRUE (CBI = LOW), otherwise the operation is a
HOLD. The carry-out (CBO) is TRUE (CBO = LOW) when
the output register (Q
7
鈥換
0
) is all HIGHs, otherwise FALSE
(CBO = HIGH). The DECREMENT operation subtracts one
from the output register when the borrow-in input is TRUE
(CBI = LOW), otherwise the operation is a HOLD. The
borrow-out (CBO) is TRUE (CBO = LOW) when the output
register (Q
7
鈥換
0
) is all LOWs, otherwise FALSE (CBO
= HIGH).
The output register (Q
7
鈥換
0
) is enabled when OE is LOW,
and disabled (HI-Z) when OE is HIGH. The output drivers will
sink the 24 mA required for many bus-interface standards.
Two or more 鈥橪S469 octal up/down counters may be cas-
caded to provide larger counters.
Features/Benefits
n
8-bit up/down counter for microprogram-counter, DMA
controller and general-purpose counting applications
n
8 bits matches byte boundaries
n
Bus-structured pinout
n
24-pin SKINNYDIP saves space
n
3-STATE outputs drive bus lines
n
Low current PNP inputs reduce loading
n
Expandable in 8-bit increments
Connection Diagram
Top View
Standard Test Load
DS008333-3
DS008333-1
Order Number DM54LS469J,
DM74LS469J or DM74LS469N
See Package Number J24F or N24C
漏 1998 Fairchild Semiconductor Corporation
DS008333
www.fairchildsemi.com

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