DM54LS461 DM74LS461 Octal Counter
July 1989
DM54LS461 DM74LS461 Octal Counter
General Description
The LS461 is an 8-bit synchronous counter with parallel
load clear and hold capability Two function select inputs
(I
0
I
1
) provide one of four operations which occur synchro-
nously on the rising edge of the clock (CK)
The LOAD operation loads the inputs (D
7
鈥揇
0
) into the out-
put register (Q
7
鈥?Q
0
) The CLEAR operation resets the out-
put register to all LOWs The HOLD operation holds the
previous value regardless of clock transitions The INCRE-
MENT operation adds one to the output register when the
carry-in input is TRUE (CI
e
LOW) otherwise the operation
is a HOLD The carry-out (CO) is TRUE (CO
e
LOW) when
the output register (Q
7
鈥換
0
) is all HIGHs otherwise FALSE
(CO
e
HIGH)
The output register (Q
7
鈥換
0
) is enabled when OE is LOW
and disabled (HI-Z) when OE is HIGH The output drivers
will sink the 24 mA required for many bus interface stand-
ards
Two or more LS461 octal counters may be cascaded to
provide larger counters The operation codes were chosen
such that when I
1
is HIGH I
0
may be used to select be-
tween LOAD and INCREMENT as in a program counter
(JUMP INCREMENT)
Features Benefits
Y
Y
Y
Y
Y
Y
Y
Octal counter for microprogram-counter DMA controller
and general purpose counting applications
8 bits match byte boundaries
Bus-structured pinout
24-pin Skinny Dip saves space
TRI-STATE outputs drive bus lines
Low current PNP inputs reduce loading
Expandable in 8-bit increments
Connection Diagram
Top View
Standard Test Load
TL L 8334 鈥?2
TL L 8334 鈥?
Order Number DM54LS461J
DM74LS461J or DM74LS461N
See NS Package Number J24F or N24C
Function Table
OE
H
L
L
L
L
L
CK
X
I1
X
L
L
H
H
H
I0
X
L
H
L
H
H
CI
X
X
X
X
H
L
D7 鈥?D0
X
X
X
D
X
X
Q7鈥?Q0
Z
L
Q
D
Q
Q plus 1
Operation
HI-Z
CLEAR
HOLD
LOAD
HOLD
INCREMENT
u
u
u
u
u
TRI-STATE is a registered trademark of National Semiconductor Corp
C
1995 National Semiconductor Corporation
TL L 8334
RRD-B30M115 Printed in U S A
1
2
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