DM74LS395 4-Bit Shift Register with TRI-STATE Outputs
February 1992
DM74LS395
4-Bit Shift Register with TRI-STATE Outputs
General Description
The LS395 is a 4-bit shift register with TRI-STATE outputs
and can operate in either a synchronous parallel load or a
serial shift-right mode as determined by the Select input An
asynchronous active LOW Master Reset (MR) input over-
rides the synchronous operations and clears the register
An active LOW Output Enable (OE) input controls the TRI-
STATE output buffers but does not interfere with the other
operations The fourth stage also has a conventional output
for linking purposes in multi-stage serial operations
Features
Y
Y
Y
Y
Shift right or parallel 4-bit register
TRI-STATE outputs
Input clamp diodes limit high speed termination effects
Fully CMOS and TTL compatible
Connection Diagram
Dual-In-Line Package
Logic Symbol
TL F 9833 鈥?2
TL F 9833 鈥?1
V
CC
e
Pin 16
GND
e
Pin 8
Order Number DM74LS395WM or DM74LS395N
See NS Package Number M16B or N16E
Mode Select Table
Operating Mode
Asynchronous Reset
Shift SET First Stage
Shift RESET First Stage
Parallel Load
L
H
H
H
Inputs
MR CP
t
n
Outputs
O1
t
n
a
1
O2
O3
S D
S
P
n
O0
X
H
L
X
X
X
L
H
X X
K
L
K
L
K
H
L
L
L
O0
n
O1
n
02
n
X L O0
n
O1
n
02
n
Pn P0 P1 P2 P3
t
n
t
n
a
1
e
Time before and after CP HIGH-to-LOW transition
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 9833
RRD-B30M115 Printed in U S A
1
2
3
4
5
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