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DM74LS366A Datasheet

  • DM74LS366A

  • Hex TRI-STATE Inverting Buffer

  • 163.11KB

  • NSC

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DM54LS366A DM74LS366A Hex TRI-STATE Inverting Buffer
September 1991
DM54LS366A DM74LS366A
Hex TRI-STATE Inverting Buffer
General Description
This device contains six independent gates each of which
performs an inverting buffer function The outputs have the
TRI-STATE feature When enabled the outputs exhibit the
low impedance characteristics of a standard LS output with
additional drive capability to permit the driving of bus lines
without external resistors When disabled both the output
transistors are turned off presenting a high-impedance state
to the bus line Thus the output will act neither as a signifi-
cant load nor as a driver To minimize the possibility that two
outputs will attempt to take a common bus to opposite logic
levels the disable time is shorter than the enable time of the
outputs
Connection Diagram
Dual-In-Line Package
TL F 6428 鈥?
Order Number DM54LS366AJ DM54LS366AW
DM54LS366AE DM74LS366AM or DM74LS366AN
See NS Package Number E20A J16A M16A N16E or W16A
Function Table
Y
e
A
Inputs
G1
H
X
L
L
G2
X
H
L
L
A
X
X
L
H
Output
Y
Hi-Z
Hi-Z
H
L
H
e
High Logic Level
L
e
Low Logic Level
X
e
Either Low or High Logic Level
Hi-Z
e
TRI-STATE (Outputs are disabled)
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 6428
RRD-B30M105 Printed in U S A

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