DM54LS259 DM74LS259 8-Bit Addressable Latches
May 1992
DM54LS259 DM74LS259 8-Bit Addressable Latches
General Description
These 8-bit addressable latches are designed for general
purpose storage applications in digital systems Specific
uses include working registers serial-holding registers and
active-high decoders or demultiplexers They are multifunc-
tional devices capable of storing single-line data in eight
addressable latches and being a 1-of-8 decoder or demulti-
plexer with active-high outputs
Four distinct modes of operation are selectable by control-
ling the clear and enable inputs as enumerated in the func-
tion table In the addressable-latch mode data at the data-
in terminal is written into the addressed latch The ad-
dressed latch will follow the data input with all unaddressed
latches remaining in their previous states In the memory
mode all latches remain in their previous states and are
unaffected by the data or address inputs To eliminate the
possibility of entering erroneous data in the latches the en-
able should be held high (inactive) while the address lines
are changing In the 1-of-8 decoding or demultiplexing
mode the addressed output will follow the level of the D
input with all other outputs low In the clear mode all out-
puts are low and unaffected by the address and data inputs
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
8-Bit parallel-out storage register performs serial-to-par-
allel conversion with storage
Asynchronous parallel clear
Active high decoder
Enable disable input simplifies expansion
Direct replacement for Fairchild 9334
Expandable for N-bit applications
Four distinct functional modes
Typical propagation delay times
Enable-to-output 18 ns
Data-to-output 16 ns
Address-to-output 21 ns
Clear-to-output 17 ns
Fan-out
I
OL
(sink current)
54LS259 4 mA
74LS259 8 mA
I
OH
(source current)
b
0 4 mA
Typical I
CC
22 mA
Connection Diagram
Dual-In-Line Package
Function Table
Inputs
Clear
H
H
L
L
E
L
H
L
H
Output of
Addressed
Latch
D
Q
i0
D
L
Each
Other
Output
Q
i0
Q
i0
L
L
Function
Addressable Latch
Memory
8-Line Demultiplexer
Clear
Latch Selection Table
Select Inputs
C
L
L
L
L
H
H
H
H
B
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
Latch
Addressed
0
1
2
3
4
5
6
7
TL F 6418 鈥?1
Order Number DM54LS259E DM54LS259J
DM54LS259W DM74LS259M
DM74LS259WM or DM74LS259N
See NS Package Number E20A J16A
M16A M16B N16E or W16A
H
e
High Level L
e
Low Level
D
e
the Level of the Data Input
Q
i0
e
the Level of Q
i
(i
e
0 1
7 as Appropriate) before the Indicated
Steady-State Input Conditions Were Established
C
1995 National Semiconductor Corporation
TL F 6418
RRD-B30M105 Printed in U S A
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