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DM74LS243N Datasheet

  • DM74LS243N

  • Quadruple Bus Transceiver

  • FAIRCHILD

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DM74LS243 Quadruple Bus Transceiver
August 1986
Revised January 2000
DM74LS243
Quadruple Bus Transceiver
General Description
This four data line transceiver is designed for asynchro-
nous two-way communications between data buses. It can
be used to drive terminated lines down to 133鈩?
Features
s
Two-way asynchronous communication between data
buses
s
PNP inputs reduce DC loading on bus line
s
Hysteresis at data inputs improves noise margin
Ordering Code:
Order Number
DM74LS243M
DM74LS243N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Function Table
Control
Inputs
G AB
H
L
H
L
I
=
Input
O
=
Output
H
=
HIGH Logic Level
L
=
LOW Logic Level
Note 1:
Possibly destructive oscillation may occur if the transceivers are
enabled in both directions at once.
Data Port
Status
GBA
H
H
L
L
I
A
O
(Note 1)
ISOLATED
O
B
I
(Note 1)
漏 2000 Fairchild Semiconductor Corporation
DS006412
www.fairchildsemi.com

DM74LS243N 產(chǎn)品屬性

  • 25

  • 集成電路 (IC)

  • 邏輯 - 緩沖器，驅動器，接收器，收發(fā)器

  • 74LS

  • 收發(fā)器，非反相

  • 1

  • 4

  • 15mA，24mA

  • 4.75 V ~ 5.25 V

  • 0°C ~ 70°C

  • 通孔

  • 14-DIP（0.300"，7.62mm）

  • 14-DIP

  • 帶卷 (TR)

  • 74LS24374LS243N

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