DM74LS197 Presettable Binary Counters
February 1992
DM74LS197 Presettable Binary Counters
General Description
The 鈥橪S197 ripple counter contains divide-by-two and di-
vide-by-eight sections which can be combined to form a
modulo-16 binary counter State changes are initiated by
the falling edge of the clock The 鈥橪S197 has a Master Re-
set (MR) input which overrides all other inputs and asyn-
chronously forces all outputs LOW A Parallel Load input
(PL) overrides clocked operations and asynchronously
loads the data on the Parallel Data inputs (P
n
) into the flip-
flops This preset feature makes the circuit usable as a pro-
grammable counter The circuit can also be used as a 4-bit
latch loading data from the Parallel Data inputs when PL is
LOW and storing the data when PL is HIGH For detail spec-
ifications and functional description please refer to the
鈥橪S196 data sheet
Features
Y
Y
Y
High counting rates Typically 70 MHz
Asynchronous preset
Asynchronous master reset
Connection Diagram
Dual-In-Line Package
TL F 10180 鈥?1
Order Number DM74LS197M or DM74LS197N
See NS Package Number M14A or N14A
Mode Select Table
Pin Names
CP0
CP1
MR
P0鈥揚3
PL
Q0
Q1鈥換3
Description
d
2 Section Clock Input
Inputs
MR
L
H
H
PL
X
L
H
CP
X
X
K
Response
Qn Forced LOW
Pn
x
Qn
Count Up
(Active Falling Edge)
d
8 Section Clock Input
(Active Falling Edge)
Asynchronous Master Reset Input
(Active LOW)
Parallel Data Inputs
Asynchronous Parallel Load Input
(Active LOW)
d
2 Section Output
d
8 Section Outputs
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Q0 output is guaranteed to drive the full rated fan-out plus the CP1 input
C
1995 National Semiconductor Corporation
TL F 10180
RRD-B30M105 Printed in U S A
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