DM74LS174 鈥?DM74LS175 Hex/Quad D-Type Flip-Flops with Clear
August 1992
Revised April 2000
DM74LS174 鈥?DM74LS175
Hex/Quad D-Type Flip-Flops with Clear
General Description
These positive-edge-triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic. All have a direct clear
input, and the quad (175) versions feature complementary
outputs from each flip-flop.
Information at the D inputs meeting the setup time require-
ments is transferred to the Q outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a partic-
ular voltage level and is not directly related to the transition
time of the positive-going pulse. When the clock input is at
either the HIGH or LOW level, the D input signal has no
effect at the output.
Features
s
DM74LS174 contains six flip-flops with single-rail
outputs
s
DM74LS175 contains four flip-flops with double-rail
outputs
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Buffered clock and direct clear inputs
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Individual data input to each flip-flop
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Applications include:
Buffer/storage registers
Shift registers
Pattern generators
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Typical clock frequency 40 MHz
s
Typical power dissipation per flip-flop 14 mW
Ordering Code:
Order Number
DM74LS174M
DM74LS174SJ
DM74LS174N
DM74LS175M
DM74LS175SJ
DM74LS175N
Package Number
M16A
M16D
N16E
M16A
M16D
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagrams
DM74LS174
DM74LS175
漏 2000 Fairchild Semiconductor Corporation
DS006404
www.fairchildsemi.com
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