DM74LS169A Synchronous 4-Bit Up/Down Binary Counter
August 1986
Revised April 2000
DM74LS169A
Synchronous 4-Bit Up/Down Binary Counter
General Description
This synchronous presettable counter features an internal
carry look-ahead for cascading in high-speed counting
applications. Synchronous operation is provided by having
all flip-flops clocked simultaneously, so that the outputs all
change at the same time when so instructed by the count-
enable inputs and internal gating. This mode of operation
helps eliminate the output counting spikes that are nor-
mally associated with asynchronous (ripple clock)
counters. A buffered clock input triggers the four master-
slave flip-flops on the rising edge of the clock waveform.
This counter is fully programmable; that is, the outputs may
each be preset either HIGH or LOW. The load input cir-
cuitry allows loading with the carry-enable output of cas-
caded counters. As loading is synchronous, setting up a
low level at the load input disables the counter and causes
the outputs to agree with the data inputs after the next
clock pulse.
The carry look-ahead circuitry permits cascading counters
for n-bit synchronous applications without additional gating.
Both count-enable inputs (P and T) must be LOW to count.
The direction of the count is determined by the level of the
UP/DOWN input. When the input is HIGH, the counter
counts UP; when LOW, it counts DOWN. Input T is fed for-
ward to enable the carry outputs. The carry output thus
enabled will produce a low-level output pulse with a dura-
tion approximately equal to the high portion of the Q
A
out-
put when counting UP, and approximately equal to the low
portion of the Q
A
output when counting DOWN. This low-
level overflow carry pulse can be used to enable succes-
sively cascaded stages. Transitions at the enable P or T
inputs are allowed regardless of the level of the clock input.
All inputs are diode clamped to minimize transmission-line
effects, thereby simplifying system design.
This counter features a fully independent clock circuit.
Changes at control inputs (enable P, enable T, load, UP/
DOWN), which modify the operating mode, have no effect
until clocking occurs. The function of the counter (whether
enabled, disabled, loading, or counting) will be dictated
solely by the conditions meeting the stable setup and hold
times.
Features
s
Fully synchronous operation for counting and
programming.
s
Internal look-ahead for fast counting.
s
Carry output for n-bit cascading.
s
Fully independent clock circuit
Ordering Code:
Order Number
DM74LS169AM
DM74LS169AN
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
漏 2000 Fairchild Semiconductor Corporation
DS006401
www.fairchildsemi.com
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